1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <netdev.h> 26 #include <asm/mmu.h> 27 #include <asm/processor.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_law.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/fsl_serdes.h> 33 #include <asm/fsl_portals.h> 34 #include <asm/fsl_liodn.h> 35 #include <malloc.h> 36 #include <fm_eth.h> 37 #include <fsl_mdio.h> 38 #include <miiphy.h> 39 #include <phy.h> 40 41 #include "../common/ngpixis.h" 42 #include "../common/fman.h" 43 #include <asm/fsl_dtsec.h> 44 45 #define EMI_NONE 0xffffffff 46 #define EMI_MASK 0xf0000000 47 #define EMI1_RGMII 0x0 48 #define EMI1_SLOT3 0x80000000 /* bank1 EFGH */ 49 #define EMI1_SLOT4 0x40000000 /* bank2 ABCD */ 50 #define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */ 51 #define EMI2_SLOT4 0x10000000 /* bank2 ABCD */ 52 #define EMI2_SLOT5 0x30000000 /* bank3 ABCD */ 53 #define EMI1_MASK 0xc0000000 54 #define EMI2_MASK 0x30000000 55 56 static int mdio_mux[NUM_FM_PORTS]; 57 58 static char *mdio_names[16] = { 59 "P4080DS_MDIO0", 60 "P4080DS_MDIO1", 61 NULL, 62 "P4080DS_MDIO3", 63 "P4080DS_MDIO4", 64 NULL, NULL, NULL, 65 "P4080DS_MDIO8", 66 NULL, NULL, NULL, 67 "P4080DS_MDIO12", 68 NULL, NULL, NULL, 69 }; 70 71 /* 72 * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means 73 * that the mapping must be determined dynamically, or that the lane maps to 74 * something other than a board slot. 75 */ 76 static u8 lane_to_slot[] = { 77 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5 78 }; 79 80 static char *p4080ds_mdio_name_for_muxval(u32 muxval) 81 { 82 return mdio_names[(muxval & EMI_MASK) >> 28]; 83 } 84 85 struct mii_dev *mii_dev_for_muxval(u32 muxval) 86 { 87 struct mii_dev *bus; 88 char *name = p4080ds_mdio_name_for_muxval(muxval); 89 90 if (!name) { 91 printf("No bus for muxval %x\n", muxval); 92 return NULL; 93 } 94 95 bus = miiphy_get_dev_by_name(name); 96 97 if (!bus) { 98 printf("No bus by name %s\n", name); 99 return NULL; 100 } 101 102 return bus; 103 } 104 105 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS) 106 int board_phy_config(struct phy_device *phydev) 107 { 108 if (phydev->drv->config) 109 phydev->drv->config(phydev); 110 if (phydev->drv->uid == PHY_UID_TN2020) { 111 unsigned long timeout = 1 * 1000; /* 1 seconds */ 112 enum srds_prtcl device; 113 114 /* 115 * Wait for the XAUI to come out of reset. This is when it 116 * starts transmitting alignment signals. 117 */ 118 while (--timeout) { 119 int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1); 120 if (reg < 0) { 121 printf("TN2020: Error reading from PHY at " 122 "address %u\n", phydev->addr); 123 break; 124 } 125 /* 126 * Note that we've never actually seen 127 * MDIO_CTRL1_RESET set to 1. 128 */ 129 if ((reg & MDIO_CTRL1_RESET) == 0) 130 break; 131 udelay(1000); 132 } 133 134 if (!timeout) { 135 printf("TN2020: Timeout waiting for PHY at address %u " 136 " to reset.\n", phydev->addr); 137 } 138 139 switch (phydev->addr) { 140 case CONFIG_SYS_FM1_10GEC1_PHY_ADDR: 141 device = XAUI_FM1; 142 break; 143 case CONFIG_SYS_FM2_10GEC1_PHY_ADDR: 144 device = XAUI_FM2; 145 break; 146 default: 147 device = NONE; 148 } 149 150 serdes_reset_rx(device); 151 } 152 153 return 0; 154 } 155 #endif 156 157 struct p4080ds_mdio { 158 u32 muxval; 159 struct mii_dev *realbus; 160 }; 161 162 static void p4080ds_mux_mdio(u32 muxval) 163 { 164 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); 165 uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK); 166 gpioval |= muxval; 167 168 out_be32(&pgpio->gpdat, gpioval); 169 } 170 171 static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad, 172 int regnum) 173 { 174 struct p4080ds_mdio *priv = bus->priv; 175 176 p4080ds_mux_mdio(priv->muxval); 177 178 return priv->realbus->read(priv->realbus, addr, devad, regnum); 179 } 180 181 static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad, 182 int regnum, u16 value) 183 { 184 struct p4080ds_mdio *priv = bus->priv; 185 186 p4080ds_mux_mdio(priv->muxval); 187 188 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); 189 } 190 191 static int p4080ds_mdio_reset(struct mii_dev *bus) 192 { 193 struct p4080ds_mdio *priv = bus->priv; 194 195 return priv->realbus->reset(priv->realbus); 196 } 197 198 static int p4080ds_mdio_init(char *realbusname, u32 muxval) 199 { 200 struct p4080ds_mdio *pmdio; 201 struct mii_dev *bus = mdio_alloc(); 202 203 if (!bus) { 204 printf("Failed to allocate P4080DS MDIO bus\n"); 205 return -1; 206 } 207 208 pmdio = malloc(sizeof(*pmdio)); 209 if (!pmdio) { 210 printf("Failed to allocate P4080DS private data\n"); 211 free(bus); 212 return -1; 213 } 214 215 bus->read = p4080ds_mdio_read; 216 bus->write = p4080ds_mdio_write; 217 bus->reset = p4080ds_mdio_reset; 218 sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval)); 219 220 pmdio->realbus = miiphy_get_dev_by_name(realbusname); 221 222 if (!pmdio->realbus) { 223 printf("No bus with name %s\n", realbusname); 224 free(bus); 225 free(pmdio); 226 return -1; 227 } 228 229 pmdio->muxval = muxval; 230 bus->priv = pmdio; 231 232 return mdio_register(bus); 233 } 234 235 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, 236 enum fm_port port, int offset) 237 { 238 if (mdio_mux[port] == EMI1_RGMII) 239 fdt_set_phy_handle(blob, prop, pa, "phy_rgmii"); 240 241 if (mdio_mux[port] == EMI1_SLOT3) { 242 int idx = port - FM2_DTSEC1 + 5; 243 char phy[16]; 244 245 sprintf(phy, "phy%d_slot3", idx); 246 247 fdt_set_phy_handle(blob, prop, pa, phy); 248 } 249 } 250 251 void fdt_fixup_board_enet(void *fdt) 252 { 253 int i; 254 255 /* 256 * P4080DS can be configured in many different ways, supporting a number 257 * of combinations of ethernet devices and phy types. In order to 258 * have just one device tree for all of those configurations, we fix up 259 * the tree here. By default, the device tree configures FM1 and FM2 260 * for SGMII, and configures XAUI on both 10G interfaces. So we have 261 * a number of different variables to track: 262 * 263 * 1) Whether the device is configured at all. Whichever devices are 264 * not enabled should be disabled by setting the "status" property 265 * to "disabled". 266 * 2) What the PHY interface is. If this is an RGMII connection, 267 * we should change the "phy-connection-type" property to 268 * "rgmii" 269 * 3) Which PHY is being used. Because the MDIO buses are muxed, 270 * we need to redirect the "phy-handle" property to point at the 271 * PHY on the right slot/bus. 272 */ 273 274 /* We've got six MDIO nodes that may or may not need to exist */ 275 fdt_status_disabled_by_alias(fdt, "emi1_slot3"); 276 fdt_status_disabled_by_alias(fdt, "emi1_slot4"); 277 fdt_status_disabled_by_alias(fdt, "emi1_slot5"); 278 fdt_status_disabled_by_alias(fdt, "emi2_slot4"); 279 fdt_status_disabled_by_alias(fdt, "emi2_slot5"); 280 281 for (i = 0; i < NUM_FM_PORTS; i++) { 282 switch (mdio_mux[i]) { 283 case EMI1_SLOT3: 284 fdt_status_okay_by_alias(fdt, "emi1_slot3"); 285 break; 286 case EMI1_SLOT4: 287 fdt_status_okay_by_alias(fdt, "emi1_slot4"); 288 break; 289 case EMI1_SLOT5: 290 fdt_status_okay_by_alias(fdt, "emi1_slot5"); 291 break; 292 case EMI2_SLOT4: 293 fdt_status_okay_by_alias(fdt, "emi2_slot4"); 294 break; 295 case EMI2_SLOT5: 296 fdt_status_okay_by_alias(fdt, "emi2_slot5"); 297 break; 298 } 299 } 300 } 301 302 int board_eth_init(bd_t *bis) 303 { 304 #ifdef CONFIG_FMAN_ENET 305 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); 306 int i; 307 struct fsl_pq_mdio_info dtsec_mdio_info; 308 struct tgec_mdio_info tgec_mdio_info; 309 310 /* Initialize the mdio_mux array so we can recognize empty elements */ 311 for (i = 0; i < NUM_FM_PORTS; i++) 312 mdio_mux[i] = EMI_NONE; 313 314 /* The first 4 GPIOs are outputs to control MDIO bus muxing */ 315 out_be32(&pgpio->gpdir, EMI_MASK); 316 317 dtsec_mdio_info.regs = 318 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; 319 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 320 321 /* Register the 1G MDIO bus */ 322 fsl_pq_mdio_init(bis, &dtsec_mdio_info); 323 324 tgec_mdio_info.regs = 325 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; 326 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 327 328 /* Register the 10G MDIO bus */ 329 fm_tgec_mdio_init(bis, &tgec_mdio_info); 330 331 /* Register the 6 muxing front-ends to the MDIO buses */ 332 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII); 333 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); 334 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); 335 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); 336 p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4); 337 p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5); 338 339 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); 340 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); 341 fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); 342 fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); 343 fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); 344 345 #if (CONFIG_SYS_NUM_FMAN == 2) 346 fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); 347 fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); 348 fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR); 349 fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR); 350 fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); 351 #endif 352 353 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 354 int idx = i - FM1_DTSEC1, lane, slot; 355 switch (fm_info_get_enet_if(i)) { 356 case PHY_INTERFACE_MODE_SGMII: 357 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); 358 if (lane < 0) 359 break; 360 slot = lane_to_slot[lane]; 361 switch (slot) { 362 case 3: 363 mdio_mux[i] = EMI1_SLOT3; 364 fm_info_set_mdio(i, 365 mii_dev_for_muxval(mdio_mux[i])); 366 break; 367 case 4: 368 mdio_mux[i] = EMI1_SLOT4; 369 fm_info_set_mdio(i, 370 mii_dev_for_muxval(mdio_mux[i])); 371 break; 372 case 5: 373 mdio_mux[i] = EMI1_SLOT5; 374 fm_info_set_mdio(i, 375 mii_dev_for_muxval(mdio_mux[i])); 376 break; 377 }; 378 break; 379 case PHY_INTERFACE_MODE_RGMII: 380 fm_info_set_phy_address(i, 0); 381 mdio_mux[i] = EMI1_RGMII; 382 fm_info_set_mdio(i, 383 mii_dev_for_muxval(mdio_mux[i])); 384 break; 385 default: 386 break; 387 } 388 } 389 390 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { 391 int idx = i - FM1_10GEC1, lane, slot; 392 switch (fm_info_get_enet_if(i)) { 393 case PHY_INTERFACE_MODE_XGMII: 394 lane = serdes_get_first_lane(XAUI_FM1 + idx); 395 if (lane < 0) 396 break; 397 slot = lane_to_slot[lane]; 398 switch (slot) { 399 case 4: 400 mdio_mux[i] = EMI2_SLOT4; 401 fm_info_set_mdio(i, 402 mii_dev_for_muxval(mdio_mux[i])); 403 break; 404 case 5: 405 mdio_mux[i] = EMI2_SLOT5; 406 fm_info_set_mdio(i, 407 mii_dev_for_muxval(mdio_mux[i])); 408 break; 409 }; 410 break; 411 default: 412 break; 413 } 414 } 415 416 #if (CONFIG_SYS_NUM_FMAN == 2) 417 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { 418 int idx = i - FM2_DTSEC1, lane, slot; 419 switch (fm_info_get_enet_if(i)) { 420 case PHY_INTERFACE_MODE_SGMII: 421 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); 422 if (lane < 0) 423 break; 424 slot = lane_to_slot[lane]; 425 switch (slot) { 426 case 3: 427 mdio_mux[i] = EMI1_SLOT3; 428 fm_info_set_mdio(i, 429 mii_dev_for_muxval(mdio_mux[i])); 430 break; 431 case 4: 432 mdio_mux[i] = EMI1_SLOT4; 433 fm_info_set_mdio(i, 434 mii_dev_for_muxval(mdio_mux[i])); 435 break; 436 case 5: 437 mdio_mux[i] = EMI1_SLOT5; 438 fm_info_set_mdio(i, 439 mii_dev_for_muxval(mdio_mux[i])); 440 break; 441 }; 442 break; 443 case PHY_INTERFACE_MODE_RGMII: 444 fm_info_set_phy_address(i, 0); 445 mdio_mux[i] = EMI1_RGMII; 446 fm_info_set_mdio(i, 447 mii_dev_for_muxval(mdio_mux[i])); 448 break; 449 default: 450 break; 451 } 452 } 453 454 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { 455 int idx = i - FM2_10GEC1, lane, slot; 456 switch (fm_info_get_enet_if(i)) { 457 case PHY_INTERFACE_MODE_XGMII: 458 lane = serdes_get_first_lane(XAUI_FM2 + idx); 459 if (lane < 0) 460 break; 461 slot = lane_to_slot[lane]; 462 switch (slot) { 463 case 4: 464 mdio_mux[i] = EMI2_SLOT4; 465 fm_info_set_mdio(i, 466 mii_dev_for_muxval(mdio_mux[i])); 467 break; 468 case 5: 469 mdio_mux[i] = EMI2_SLOT5; 470 fm_info_set_mdio(i, 471 mii_dev_for_muxval(mdio_mux[i])); 472 break; 473 }; 474 break; 475 default: 476 break; 477 } 478 } 479 #endif 480 481 cpu_eth_init(bis); 482 #endif /* CONFIG_FMAN_ENET */ 483 484 return pci_eth_init(bis); 485 } 486