1 /*
2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
3  * Author: Timur Tabi <timur@freescale.com>
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23 
24 /*
25  * This file handles the board muxing between the Fman Ethernet MACs and
26  * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference
27  * board. The RGMII PHYs are the two on-board 1Gb ports.  The SGMII PHYs are
28  * provided by the standard Freescale four-port SGMII riser card.  The 10Gb
29  * XGMII PHY is provided via the XAUI riser card.  Since there is only one
30  * Fman device on a P3041 and P5020, we only support one SGMII card and one
31  * RGMII card.
32  *
33  * Muxing is handled via the PIXIS BRDCFG1 register.  The EMI1 bits control
34  * muxing among the RGMII PHYs and the SGMII PHYs.  The value for RGMII is
35  * always the same (0).  The value for SGMII depends on which slot the riser is
36  * inserted in.  The EMI2 bits control muxing for the the XGMII.  Like SGMII,
37  * the value is based on which slot the XAUI is inserted in.
38  *
39  * The SERDES configuration is used to determine where the SGMII and XAUI cards
40  * exist, and also which Fman MACs are routed to which PHYs.  So for a given
41  * Fman MAC, there is one and only PHY it connects to.  MACs cannot be routed
42  * to PHYs dynamically.
43  *
44  *
45  * This file also updates the device tree in three ways:
46  *
47  * 1) The status of each virtual MDIO node that is referenced by an Ethernet
48  *    node is set to "okay".
49  *
50  * 2) The phy-handle property of each active Ethernet MAC node is set to the
51  *    appropriate PHY node.
52  *
53  * 3) The "mux value" for each virtual MDIO node is set to the correct value,
54  *    if necessary.  Some virtual MDIO nodes do not have configurable mux
55  *    values, so those values are hard-coded in the DTS.  On the HYDRA board,
56  *    the virtual MDIO node for the SGMII card needs to be updated.
57  *
58  * For all this to work, the device tree needs to have the following:
59  *
60  * 1) An alias for each PHY node that an Ethernet node could be routed to.
61  *
62  * 2) An alias for each real and virtual MDIO node that is disabled by default
63  * and might need to be enabled, and also might need to have its mux-value
64  * updated.
65  */
66 
67 #include <common.h>
68 #include <netdev.h>
69 #include <asm/fsl_serdes.h>
70 #include <fm_eth.h>
71 #include <fsl_mdio.h>
72 #include <malloc.h>
73 #include <fdt_support.h>
74 #include <asm/fsl_dtsec.h>
75 
76 #include "../common/ngpixis.h"
77 #include "../common/fman.h"
78 
79 #ifdef CONFIG_FMAN_ENET
80 
81 #define BRDCFG1_EMI1_SEL_MASK	0x70
82 #define BRDCFG1_EMI1_SEL_SLOT1	0x10
83 #define BRDCFG1_EMI1_SEL_SLOT2	0x20
84 #define BRDCFG1_EMI1_SEL_SLOT5	0x30
85 #define BRDCFG1_EMI1_SEL_SLOT6	0x40
86 #define BRDCFG1_EMI1_SEL_SLOT7	0x50
87 #define BRDCFG1_EMI1_SEL_RGMII	0x00
88 #define BRDCFG1_EMI1_EN		0x08
89 #define BRDCFG1_EMI2_SEL_MASK	0x06
90 #define BRDCFG1_EMI2_SEL_SLOT1	0x00
91 #define BRDCFG1_EMI2_SEL_SLOT2	0x02
92 
93 #define BRDCFG2_REG_GPIO_SEL	0x20
94 
95 /*
96  * BRDCFG1 mask and value for each MAC
97  *
98  * This array contains the BRDCFG1 values (in mask/val format) that route the
99  * MDIO bus to a particular RGMII or SGMII PHY.
100  */
101 struct {
102 	u8 mask;
103 	u8 val;
104 } mdio_mux[NUM_FM_PORTS];
105 
106 /*
107  * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
108  * that the mapping must be determined dynamically, or that the lane maps to
109  * something other than a board slot
110  */
111 static u8 lane_to_slot[] = {
112 	7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
113 };
114 
115 /*
116  * Set the board muxing for a given MAC
117  *
118  * The MDIO layer calls this function every time it wants to talk to a PHY.
119  */
120 void hydra_mux_mdio(u8 mask, u8 val)
121 {
122 	clrsetbits_8(&pixis->brdcfg1, mask, val);
123 }
124 
125 struct hydra_mdio {
126 	u8 mask;
127 	u8 val;
128 	struct mii_dev *realbus;
129 };
130 
131 static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
132 				int regnum)
133 {
134 	struct hydra_mdio *priv = bus->priv;
135 
136 	hydra_mux_mdio(priv->mask, priv->val);
137 
138 	return priv->realbus->read(priv->realbus, addr, devad, regnum);
139 }
140 
141 static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
142 				int regnum, u16 value)
143 {
144 	struct hydra_mdio *priv = bus->priv;
145 
146 	hydra_mux_mdio(priv->mask, priv->val);
147 
148 	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
149 }
150 
151 static int hydra_mdio_reset(struct mii_dev *bus)
152 {
153 	struct hydra_mdio *priv = bus->priv;
154 
155 	return priv->realbus->reset(priv->realbus);
156 }
157 
158 static void hydra_mdio_set_mux(char *name, u8 mask, u8 val)
159 {
160 	struct mii_dev *bus = miiphy_get_dev_by_name(name);
161 	struct hydra_mdio *priv = bus->priv;
162 
163 	priv->mask = mask;
164 	priv->val = val;
165 }
166 
167 static int hydra_mdio_init(char *realbusname, char *fakebusname)
168 {
169 	struct hydra_mdio *hmdio;
170 	struct mii_dev *bus = mdio_alloc();
171 
172 	if (!bus) {
173 		printf("Failed to allocate Hydra MDIO bus\n");
174 		return -1;
175 	}
176 
177 	hmdio = malloc(sizeof(*hmdio));
178 	if (!hmdio) {
179 		printf("Failed to allocate Hydra private data\n");
180 		free(bus);
181 		return -1;
182 	}
183 
184 	bus->read = hydra_mdio_read;
185 	bus->write = hydra_mdio_write;
186 	bus->reset = hydra_mdio_reset;
187 	sprintf(bus->name, fakebusname);
188 
189 	hmdio->realbus = miiphy_get_dev_by_name(realbusname);
190 
191 	if (!hmdio->realbus) {
192 		printf("No bus with name %s\n", realbusname);
193 		free(bus);
194 		free(hmdio);
195 		return -1;
196 	}
197 
198 	bus->priv = hmdio;
199 
200 	return mdio_register(bus);
201 }
202 
203 /*
204  * Given an alias or a path for a node, set the mux value of that node.
205  *
206  * If 'alias' is not a valid alias, then it is treated as a full path to the
207  * node.  No error checking is performed.
208  *
209  * This function is normally called to set the fsl,hydra-mdio-muxval property
210  * of a virtual MDIO node.
211  */
212 static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
213 {
214 	const char *path = fdt_get_alias(fdt, alias);
215 
216 	if (!path)
217 		path = alias;
218 
219 	do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
220 			 &mux, sizeof(mux), 1);
221 }
222 
223 /*
224  * Given the following ...
225  *
226  * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
227  * compatible string and 'addr' physical address)
228  *
229  * 2) An Fman port
230  *
231  * ... update the phy-handle property of the Ethernet node to point to the
232  * right PHY.  This assumes that we already know the PHY for each port.  That
233  * information is stored in mdio_mux[].
234  *
235  * The offset of the Fman Ethernet node is also passed in for convenience, but
236  * it is not used, and we recalculate the offset anyway.
237  *
238  * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
239  * Inside the Fman, "ports" are things that connect to MACs.  We only call them
240  * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
241  * and ports are the same thing.
242  *
243  * Note that this code would be cleaner if had a function called
244  * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[]
245  * array.  That's because all we're doing is figuring out the PHY address for
246  * a given Fman MAC and writing it to the device tree.  Well, we already did
247  * the hard work to figure that out in board_eth_init(), so it's silly to
248  * repeat that here.
249  */
250 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
251 			      enum fm_port port, int offset)
252 {
253 	unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask;
254 	char phy[16];
255 
256 	if (port == FM1_10GEC1) {
257 		/* XAUI */
258 		int lane = serdes_get_first_lane(XAUI_FM1);
259 		if (lane >= 0) {
260 			/* The XAUI PHY is identified by the slot */
261 			sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
262 			fdt_set_phy_handle(fdt, compat, addr, phy);
263 		}
264 		return;
265 	}
266 
267 	if (mux == BRDCFG1_EMI1_SEL_RGMII) {
268 		/* RGMII */
269 		/* The RGMII PHY is identified by the MAC connected to it */
270 		sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
271 		fdt_set_phy_handle(fdt, compat, addr, phy);
272 	}
273 
274 	/* If it's not RGMII or XGMII, it must be SGMII */
275 	if (mux) {
276 		/* The SGMII PHY is identified by the MAC connected to it */
277 		sprintf(phy, "phy_sgmii_%x",
278 			CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1));
279 		fdt_set_phy_handle(fdt, compat, addr, phy);
280 	}
281 }
282 
283 #define PIXIS_SW2_LANE_23_SEL		0x80
284 #define PIXIS_SW2_LANE_45_SEL		0x40
285 #define PIXIS_SW2_LANE_67_SEL_MASK	0x30
286 #define PIXIS_SW2_LANE_67_SEL_5		0x00
287 #define PIXIS_SW2_LANE_67_SEL_6		0x20
288 #define PIXIS_SW2_LANE_67_SEL_7		0x10
289 #define PIXIS_SW2_LANE_8_SEL		0x08
290 #define PIXIS_SW2_LANE_1617_SEL		0x04
291 
292 /*
293  * Initialize the lane_to_slot[] array.
294  *
295  * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
296  * slots is hard-coded.  On the Hydra board, however, the mapping is controlled
297  * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
298  * initialized.
299  */
300 static void initialize_lane_to_slot(void)
301 {
302 	u8 sw2 = in_8(&PIXIS_SW(2));
303 
304 	lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
305 	lane_to_slot[3] = lane_to_slot[2];
306 
307 	lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
308 	lane_to_slot[5] = lane_to_slot[4];
309 
310 	switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
311 	case PIXIS_SW2_LANE_67_SEL_5:
312 		lane_to_slot[6] = 5;
313 		break;
314 	case PIXIS_SW2_LANE_67_SEL_6:
315 		lane_to_slot[6] = 6;
316 		break;
317 	case PIXIS_SW2_LANE_67_SEL_7:
318 		lane_to_slot[6] = 7;
319 		break;
320 	}
321 	lane_to_slot[7] = lane_to_slot[6];
322 
323 	lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
324 
325 	lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
326 	lane_to_slot[17] = lane_to_slot[16];
327 }
328 
329 #endif /* #ifdef CONFIG_FMAN_ENET */
330 
331 /*
332  * Configure the status for the virtual MDIO nodes
333  *
334  * Rather than create the virtual MDIO nodes from scratch for each active
335  * virtual MDIO, we expect the DTS to have the nodes defined already, and we
336  * only enable the ones that are actually active.
337  *
338  * We assume that the DTS already hard-codes the status for all the
339  * virtual MDIO nodes to "disabled", so all we need to do is enable the
340  * active ones.
341  *
342  * For SGMII, we also need to set the mux value in the node.
343  */
344 void fdt_fixup_board_enet(void *fdt)
345 {
346 #ifdef CONFIG_FMAN_ENET
347 	unsigned int i;
348 	int lane;
349 
350 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
351 		int idx = i - FM1_DTSEC1;
352 
353 		switch (fm_info_get_enet_if(i)) {
354 		case PHY_INTERFACE_MODE_SGMII:
355 			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
356 			if (lane >= 0) {
357 				fdt_status_okay_by_alias(fdt, "emi1_sgmii");
358 				/* Also set the MUX value */
359 				fdt_set_mdio_mux(fdt, "emi1_sgmii",
360 						 mdio_mux[i].val);
361 			}
362 			break;
363 		case PHY_INTERFACE_MODE_RGMII:
364 			fdt_status_okay_by_alias(fdt, "emi1_rgmii");
365 			break;
366 		default:
367 			break;
368 		}
369 	}
370 
371 	lane = serdes_get_first_lane(XAUI_FM1);
372 	if (lane >= 0)
373 		fdt_status_okay_by_alias(fdt, "emi2_xgmii");
374 #endif
375 }
376 
377 int board_eth_init(bd_t *bis)
378 {
379 #ifdef CONFIG_FMAN_ENET
380 	struct fsl_pq_mdio_info dtsec_mdio_info;
381 	struct tgec_mdio_info tgec_mdio_info;
382 	unsigned int i, slot;
383 	int lane;
384 
385 	printf("Initializing Fman\n");
386 
387 	initialize_lane_to_slot();
388 
389 	/* We want to use the PIXIS to configure MUX routing, not GPIOs. */
390 	setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
391 
392 	memset(mdio_mux, 0, sizeof(mdio_mux));
393 
394 	dtsec_mdio_info.regs =
395 		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
396 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
397 
398 	/* Register the real 1G MDIO bus */
399 	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
400 
401 	tgec_mdio_info.regs =
402 		(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
403 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
404 
405 	/* Register the real 10G MDIO bus */
406 	fm_tgec_mdio_init(bis, &tgec_mdio_info);
407 
408 	/* Register the three virtual MDIO front-ends */
409 	hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO");
410 	hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO");
411 
412 	/*
413 	 * Program the DTSEC PHY addresses assuming that they are all SGMII.
414 	 * For any DTSEC that's RGMII, we'll override its PHY address later.
415 	 * We assume that DTSEC5 is only used for RGMII.
416 	 */
417 	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
418 	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
419 	fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
420 	fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
421 
422 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
423 		int idx = i - FM1_DTSEC1;
424 
425 		switch (fm_info_get_enet_if(i)) {
426 		case PHY_INTERFACE_MODE_SGMII:
427 			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
428 			if (lane < 0)
429 				break;
430 			slot = lane_to_slot[lane];
431 			mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
432 			switch (slot) {
433 			case 1:
434 				/* Always DTSEC5 on Bank 3 */
435 				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
436 						  BRDCFG1_EMI1_EN;
437 				break;
438 			case 2:
439 				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
440 						  BRDCFG1_EMI1_EN;
441 				break;
442 			case 5:
443 				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
444 						  BRDCFG1_EMI1_EN;
445 				break;
446 			case 6:
447 				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
448 						  BRDCFG1_EMI1_EN;
449 				break;
450 			case 7:
451 				mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
452 						  BRDCFG1_EMI1_EN;
453 				break;
454 			};
455 
456 			hydra_mdio_set_mux("HYDRA_SGMII_MDIO",
457 					mdio_mux[i].mask, mdio_mux[i].val);
458 			fm_info_set_mdio(i,
459 				miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
460 			break;
461 		case PHY_INTERFACE_MODE_RGMII:
462 			/*
463 			 * If DTSEC4 is RGMII, then it's routed via via EC1 to
464 			 * the first on-board RGMII port.  If DTSEC5 is RGMII,
465 			 * then it's routed via via EC2 to the second on-board
466 			 * RGMII port. The other DTSECs cannot be routed to
467 			 * RGMII.
468 			 */
469 			fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1);
470 			mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
471 			mdio_mux[i].val  = BRDCFG1_EMI1_SEL_RGMII |
472 					   BRDCFG1_EMI1_EN;
473 			hydra_mdio_set_mux("HYDRA_RGMII_MDIO",
474 					mdio_mux[i].mask, mdio_mux[i].val);
475 			fm_info_set_mdio(i,
476 				miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
477 			break;
478 		case PHY_INTERFACE_MODE_NONE:
479 			fm_info_set_phy_address(i, 0);
480 			break;
481 		default:
482 			printf("Fman1: DTSEC%u set to unknown interface %i\n",
483 			       idx + 1, fm_info_get_enet_if(i));
484 			fm_info_set_phy_address(i, 0);
485 			break;
486 		}
487 	}
488 
489 	/*
490 	 * For 10G, we only support one XAUI card per Fman.  If present, then we
491 	 * force its routing and never touch those bits again, which removes the
492 	 * need for Linux to do any muxing.  This works because of the way
493 	 * BRDCFG1 is defined, but it's a bit hackish.
494 	 *
495 	 * The PHY address for the XAUI card depends on which slot it's in. The
496 	 * macros we use imply that the PHY address is based on which FM, but
497 	 * that's not true.  On the P4080DS, FM1 could only use XAUI in slot 5,
498 	 * and FM2 could only use a XAUI in slot 4.  On the Hydra board, we
499 	 * check the actual slot and just use the macros as-is, even though
500 	 * the P3041 and P5020 only have one Fman.
501 	 */
502 	lane = serdes_get_first_lane(XAUI_FM1);
503 	if (lane >= 0) {
504 		slot = lane_to_slot[lane];
505 		if (slot == 1) {
506 			/* XAUI card is in slot 1 */
507 			clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
508 				     BRDCFG1_EMI2_SEL_SLOT1);
509 			fm_info_set_phy_address(FM1_10GEC1,
510 						CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
511 		} else {
512 			/* XAUI card is in slot 2 */
513 			clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
514 				     BRDCFG1_EMI2_SEL_SLOT2);
515 			fm_info_set_phy_address(FM1_10GEC1,
516 						CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
517 		}
518 	}
519 
520 	fm_info_set_mdio(FM1_10GEC1,
521 			miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
522 
523 	cpu_eth_init(bis);
524 #endif
525 
526 	return pci_eth_init(bis);
527 }
528