1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * Author: Timur Tabi <timur@freescale.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * This file handles the board muxing between the Fman Ethernet MACs and 26 * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference 27 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are 28 * provided by the standard Freescale four-port SGMII riser card. The 10Gb 29 * XGMII PHY is provided via the XAUI riser card. Since there is only one 30 * Fman device on a P3041 and P5020, we only support one SGMII card and one 31 * RGMII card. 32 * 33 * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control 34 * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is 35 * always the same (0). The value for SGMII depends on which slot the riser is 36 * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, 37 * the value is based on which slot the XAUI is inserted in. 38 * 39 * The SERDES configuration is used to determine where the SGMII and XAUI cards 40 * exist, and also which Fman MACs are routed to which PHYs. So for a given 41 * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed 42 * to PHYs dynamically. 43 * 44 * 45 * This file also updates the device tree in three ways: 46 * 47 * 1) The status of each virtual MDIO node that is referenced by an Ethernet 48 * node is set to "okay". 49 * 50 * 2) The phy-handle property of each active Ethernet MAC node is set to the 51 * appropriate PHY node. 52 * 53 * 3) The "mux value" for each virtual MDIO node is set to the correct value, 54 * if necessary. Some virtual MDIO nodes do not have configurable mux 55 * values, so those values are hard-coded in the DTS. On the HYDRA board, 56 * the virtual MDIO node for the SGMII card needs to be updated. 57 * 58 * For all this to work, the device tree needs to have the following: 59 * 60 * 1) An alias for each PHY node that an Ethernet node could be routed to. 61 * 62 * 2) An alias for each real and virtual MDIO node that is disabled by default 63 * and might need to be enabled, and also might need to have its mux-value 64 * updated. 65 */ 66 67 #include <common.h> 68 #include <netdev.h> 69 #include <asm/fsl_serdes.h> 70 #include <fm_eth.h> 71 #include <fsl_mdio.h> 72 #include <malloc.h> 73 #include <asm/fsl_dtsec.h> 74 75 #include "../common/ngpixis.h" 76 #include "../common/fman.h" 77 78 #ifdef CONFIG_FMAN_ENET 79 80 #define BRDCFG1_EMI1_SEL_MASK 0x70 81 #define BRDCFG1_EMI1_SEL_SLOT1 0x10 82 #define BRDCFG1_EMI1_SEL_SLOT2 0x20 83 #define BRDCFG1_EMI1_SEL_SLOT5 0x30 84 #define BRDCFG1_EMI1_SEL_SLOT6 0x40 85 #define BRDCFG1_EMI1_SEL_SLOT7 0x50 86 #define BRDCFG1_EMI1_SEL_RGMII 0x00 87 #define BRDCFG1_EMI1_EN 0x08 88 #define BRDCFG1_EMI2_SEL_MASK 0x06 89 #define BRDCFG1_EMI2_SEL_SLOT1 0x00 90 #define BRDCFG1_EMI2_SEL_SLOT2 0x02 91 92 #define BRDCFG2_REG_GPIO_SEL 0x20 93 94 /* 95 * BRDCFG1 mask and value for each MAC 96 * 97 * This array contains the BRDCFG1 values (in mask/val format) that route the 98 * MDIO bus to a particular RGMII or SGMII PHY. 99 */ 100 struct { 101 u8 mask; 102 u8 val; 103 } mdio_mux[NUM_FM_PORTS]; 104 105 /* 106 * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means 107 * that the mapping must be determined dynamically, or that the lane maps to 108 * something other than a board slot 109 */ 110 static u8 lane_to_slot[] = { 111 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0 112 }; 113 114 /* 115 * Set the board muxing for a given MAC 116 * 117 * The MDIO layer calls this function every time it wants to talk to a PHY. 118 */ 119 void hydra_mux_mdio(u8 mask, u8 val) 120 { 121 clrsetbits_8(&pixis->brdcfg1, mask, val); 122 } 123 124 struct hydra_mdio { 125 u8 mask; 126 u8 val; 127 struct mii_dev *realbus; 128 }; 129 130 static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad, 131 int regnum) 132 { 133 struct hydra_mdio *priv = bus->priv; 134 135 hydra_mux_mdio(priv->mask, priv->val); 136 137 return priv->realbus->read(priv->realbus, addr, devad, regnum); 138 } 139 140 static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad, 141 int regnum, u16 value) 142 { 143 struct hydra_mdio *priv = bus->priv; 144 145 hydra_mux_mdio(priv->mask, priv->val); 146 147 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); 148 } 149 150 static int hydra_mdio_reset(struct mii_dev *bus) 151 { 152 struct hydra_mdio *priv = bus->priv; 153 154 return priv->realbus->reset(priv->realbus); 155 } 156 157 static void hydra_mdio_set_mux(char *name, u8 mask, u8 val) 158 { 159 struct mii_dev *bus = miiphy_get_dev_by_name(name); 160 struct hydra_mdio *priv = bus->priv; 161 162 priv->mask = mask; 163 priv->val = val; 164 } 165 166 static int hydra_mdio_init(char *realbusname, char *fakebusname) 167 { 168 struct hydra_mdio *hmdio; 169 struct mii_dev *bus = mdio_alloc(); 170 171 if (!bus) { 172 printf("Failed to allocate Hydra MDIO bus\n"); 173 return -1; 174 } 175 176 hmdio = malloc(sizeof(*hmdio)); 177 if (!hmdio) { 178 printf("Failed to allocate Hydra private data\n"); 179 free(bus); 180 return -1; 181 } 182 183 bus->read = hydra_mdio_read; 184 bus->write = hydra_mdio_write; 185 bus->reset = hydra_mdio_reset; 186 sprintf(bus->name, fakebusname); 187 188 hmdio->realbus = miiphy_get_dev_by_name(realbusname); 189 190 if (!hmdio->realbus) { 191 printf("No bus with name %s\n", realbusname); 192 free(bus); 193 free(hmdio); 194 return -1; 195 } 196 197 bus->priv = hmdio; 198 199 return mdio_register(bus); 200 } 201 202 /* 203 * Given an alias or a path for a node, set the status of that node. 204 * 205 * If 'alias' is not a valid alias, then it is treated as a full path to the 206 * node. No error checking is performed. 207 * 208 * This function is normally called to set the status for a virtual MDIO node. 209 */ 210 static void fdt_set_node_status(void *fdt, const char *alias, 211 const char *status) 212 { 213 const char *path = fdt_get_alias(fdt, alias); 214 215 if (!path) 216 path = alias; 217 218 do_fixup_by_path(fdt, path, "status", status, strlen(status) + 1, 1); 219 } 220 221 /* 222 * Given an alias or a path for a node, set the mux value of that node. 223 * 224 * If 'alias' is not a valid alias, then it is treated as a full path to the 225 * node. No error checking is performed. 226 * 227 * This function is normally called to set the fsl,hydra-mdio-muxval property 228 * of a virtual MDIO node. 229 */ 230 static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux) 231 { 232 const char *path = fdt_get_alias(fdt, alias); 233 234 if (!path) 235 path = alias; 236 237 do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval", 238 &mux, sizeof(mux), 1); 239 } 240 241 /* 242 * Given the following ... 243 * 244 * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' 245 * compatible string and 'addr' physical address) 246 * 247 * 2) An Fman port 248 * 249 * ... update the phy-handle property of the Ethernet node to point to the 250 * right PHY. This assumes that we already know the PHY for each port. That 251 * information is stored in mdio_mux[]. 252 * 253 * The offset of the Fman Ethernet node is also passed in for convenience, but 254 * it is not used, and we recalculate the offset anyway. 255 * 256 * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. 257 * Inside the Fman, "ports" are things that connect to MACs. We only call them 258 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs 259 * and ports are the same thing. 260 * 261 * Note that this code would be cleaner if had a function called 262 * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[] 263 * array. That's because all we're doing is figuring out the PHY address for 264 * a given Fman MAC and writing it to the device tree. Well, we already did 265 * the hard work to figure that out in board_eth_init(), so it's silly to 266 * repeat that here. 267 */ 268 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, 269 enum fm_port port, int offset) 270 { 271 unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask; 272 char phy[16]; 273 274 if (port == FM1_10GEC1) { 275 /* XAUI */ 276 int lane = serdes_get_first_lane(XAUI_FM1); 277 if (lane >= 0) { 278 /* The XAUI PHY is identified by the slot */ 279 sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); 280 fdt_set_phy_handle(fdt, compat, addr, phy); 281 } 282 return; 283 } 284 285 if (mux == BRDCFG1_EMI1_SEL_RGMII) { 286 /* RGMII */ 287 /* The RGMII PHY is identified by the MAC connected to it */ 288 sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1); 289 fdt_set_phy_handle(fdt, compat, addr, phy); 290 } 291 292 /* If it's not RGMII or XGMII, it must be SGMII */ 293 if (mux) { 294 /* The SGMII PHY is identified by the MAC connected to it */ 295 sprintf(phy, "phy_sgmii_%x", 296 CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1)); 297 fdt_set_phy_handle(fdt, compat, addr, phy); 298 } 299 } 300 301 #define PIXIS_SW2_LANE_23_SEL 0x80 302 #define PIXIS_SW2_LANE_45_SEL 0x40 303 #define PIXIS_SW2_LANE_67_SEL_MASK 0x30 304 #define PIXIS_SW2_LANE_67_SEL_5 0x00 305 #define PIXIS_SW2_LANE_67_SEL_6 0x20 306 #define PIXIS_SW2_LANE_67_SEL_7 0x10 307 #define PIXIS_SW2_LANE_8_SEL 0x08 308 #define PIXIS_SW2_LANE_1617_SEL 0x04 309 310 /* 311 * Initialize the lane_to_slot[] array. 312 * 313 * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board 314 * slots is hard-coded. On the Hydra board, however, the mapping is controlled 315 * by board switch SW2, so the lane_to_slot[] array needs to be dynamically 316 * initialized. 317 */ 318 static void initialize_lane_to_slot(void) 319 { 320 u8 sw2 = in_8(&PIXIS_SW(2)); 321 322 lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; 323 lane_to_slot[3] = lane_to_slot[2]; 324 325 lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; 326 lane_to_slot[5] = lane_to_slot[4]; 327 328 switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { 329 case PIXIS_SW2_LANE_67_SEL_5: 330 lane_to_slot[6] = 5; 331 break; 332 case PIXIS_SW2_LANE_67_SEL_6: 333 lane_to_slot[6] = 6; 334 break; 335 case PIXIS_SW2_LANE_67_SEL_7: 336 lane_to_slot[6] = 7; 337 break; 338 } 339 lane_to_slot[7] = lane_to_slot[6]; 340 341 lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; 342 343 lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; 344 lane_to_slot[17] = lane_to_slot[16]; 345 } 346 347 #endif /* #ifdef CONFIG_FMAN_ENET */ 348 349 /* 350 * Configure the status for the virtual MDIO nodes 351 * 352 * Rather than create the virtual MDIO nodes from scratch for each active 353 * virtual MDIO, we expect the DTS to have the nodes defined already, and we 354 * only enable the ones that are actually active. 355 * 356 * We assume that the DTS already hard-codes the status for all the 357 * virtual MDIO nodes to "disabled", so all we need to do is enable the 358 * active ones. 359 * 360 * For SGMII, we also need to set the mux value in the node. 361 */ 362 void fdt_fixup_board_enet(void *fdt) 363 { 364 #ifdef CONFIG_FMAN_ENET 365 unsigned int i; 366 int lane; 367 368 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 369 int idx = i - FM1_DTSEC1; 370 371 switch (fm_info_get_enet_if(i)) { 372 case PHY_INTERFACE_MODE_SGMII: 373 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); 374 if (lane >= 0) { 375 fdt_set_node_status(fdt, "emi1_sgmii", "okay"); 376 /* Also set the MUX value */ 377 fdt_set_mdio_mux(fdt, "emi1_sgmii", 378 mdio_mux[i].val); 379 } 380 break; 381 case PHY_INTERFACE_MODE_RGMII: 382 fdt_set_node_status(fdt, "emi1_rgmii", "okay"); 383 break; 384 default: 385 break; 386 } 387 } 388 389 lane = serdes_get_first_lane(XAUI_FM1); 390 if (lane >= 0) 391 fdt_set_node_status(fdt, "emi2_xgmii", "okay"); 392 #endif 393 } 394 395 int board_eth_init(bd_t *bis) 396 { 397 #ifdef CONFIG_FMAN_ENET 398 struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; 399 struct fsl_pq_mdio_info dtsec_mdio_info; 400 struct tgec_mdio_info tgec_mdio_info; 401 unsigned int i, slot; 402 int lane; 403 404 printf("Initializing Fman\n"); 405 406 initialize_lane_to_slot(); 407 408 /* 409 * Set TBIPA on FM1@DTSEC1. This is needed for configurations 410 * where FM1@DTSEC1 isn't used directly, since it provides 411 * MDIO for other ports. 412 */ 413 out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); 414 415 /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ 416 setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); 417 418 memset(mdio_mux, 0, sizeof(mdio_mux)); 419 420 dtsec_mdio_info.regs = 421 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; 422 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 423 424 /* Register the real 1G MDIO bus */ 425 fsl_pq_mdio_init(bis, &dtsec_mdio_info); 426 427 tgec_mdio_info.regs = 428 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; 429 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 430 431 /* Register the real 10G MDIO bus */ 432 fm_tgec_mdio_init(bis, &tgec_mdio_info); 433 434 /* Register the three virtual MDIO front-ends */ 435 hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO"); 436 hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO"); 437 438 /* 439 * Program the DTSEC PHY addresses assuming that they are all SGMII. 440 * For any DTSEC that's RGMII, we'll override its PHY address later. 441 * We assume that DTSEC5 is only used for RGMII. 442 */ 443 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); 444 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); 445 fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); 446 fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); 447 448 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 449 int idx = i - FM1_DTSEC1; 450 451 switch (fm_info_get_enet_if(i)) { 452 case PHY_INTERFACE_MODE_SGMII: 453 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); 454 if (lane < 0) 455 break; 456 slot = lane_to_slot[lane]; 457 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; 458 switch (slot) { 459 case 1: 460 /* Always DTSEC5 on Bank 3 */ 461 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | 462 BRDCFG1_EMI1_EN; 463 break; 464 case 2: 465 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | 466 BRDCFG1_EMI1_EN; 467 break; 468 case 5: 469 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | 470 BRDCFG1_EMI1_EN; 471 break; 472 case 6: 473 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | 474 BRDCFG1_EMI1_EN; 475 break; 476 case 7: 477 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | 478 BRDCFG1_EMI1_EN; 479 break; 480 }; 481 482 hydra_mdio_set_mux("HYDRA_SGMII_MDIO", 483 mdio_mux[i].mask, mdio_mux[i].val); 484 fm_info_set_mdio(i, 485 miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); 486 break; 487 case PHY_INTERFACE_MODE_RGMII: 488 /* 489 * If DTSEC4 is RGMII, then it's routed via via EC1 to 490 * the first on-board RGMII port. If DTSEC5 is RGMII, 491 * then it's routed via via EC2 to the second on-board 492 * RGMII port. The other DTSECs cannot be routed to 493 * RGMII. 494 */ 495 fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1); 496 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; 497 mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | 498 BRDCFG1_EMI1_EN; 499 hydra_mdio_set_mux("HYDRA_RGMII_MDIO", 500 mdio_mux[i].mask, mdio_mux[i].val); 501 fm_info_set_mdio(i, 502 miiphy_get_dev_by_name("HYDRA_RGMII_MDIO")); 503 break; 504 case PHY_INTERFACE_MODE_NONE: 505 fm_info_set_phy_address(i, 0); 506 break; 507 default: 508 printf("Fman1: DTSEC%u set to unknown interface %i\n", 509 idx + 1, fm_info_get_enet_if(i)); 510 fm_info_set_phy_address(i, 0); 511 break; 512 } 513 } 514 515 /* 516 * For 10G, we only support one XAUI card per Fman. If present, then we 517 * force its routing and never touch those bits again, which removes the 518 * need for Linux to do any muxing. This works because of the way 519 * BRDCFG1 is defined, but it's a bit hackish. 520 * 521 * The PHY address for the XAUI card depends on which slot it's in. The 522 * macros we use imply that the PHY address is based on which FM, but 523 * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, 524 * and FM2 could only use a XAUI in slot 4. On the Hydra board, we 525 * check the actual slot and just use the macros as-is, even though 526 * the P3041 and P5020 only have one Fman. 527 */ 528 lane = serdes_get_first_lane(XAUI_FM1); 529 if (lane >= 0) { 530 slot = lane_to_slot[lane]; 531 if (slot == 1) { 532 /* XAUI card is in slot 1 */ 533 clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, 534 BRDCFG1_EMI2_SEL_SLOT1); 535 fm_info_set_phy_address(FM1_10GEC1, 536 CONFIG_SYS_FM1_10GEC1_PHY_ADDR); 537 } else { 538 /* XAUI card is in slot 2 */ 539 clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, 540 BRDCFG1_EMI2_SEL_SLOT2); 541 fm_info_set_phy_address(FM1_10GEC1, 542 CONFIG_SYS_FM2_10GEC1_PHY_ADDR); 543 } 544 } 545 546 fm_info_set_mdio(FM1_10GEC1, 547 miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); 548 549 cpu_eth_init(bis); 550 #endif 551 552 return pci_eth_init(bis); 553 } 554