1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * Author: Timur Tabi <timur@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * This file handles the board muxing between the Fman Ethernet MACs and 10 * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference 11 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are 12 * provided by the standard Freescale four-port SGMII riser card. The 10Gb 13 * XGMII PHY is provided via the XAUI riser card. Since there is only one 14 * Fman device on a P3041 and P5020, we only support one SGMII card and one 15 * RGMII card. 16 * 17 * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control 18 * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is 19 * always the same (0). The value for SGMII depends on which slot the riser is 20 * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, 21 * the value is based on which slot the XAUI is inserted in. 22 * 23 * The SERDES configuration is used to determine where the SGMII and XAUI cards 24 * exist, and also which Fman MACs are routed to which PHYs. So for a given 25 * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed 26 * to PHYs dynamically. 27 * 28 * 29 * This file also updates the device tree in three ways: 30 * 31 * 1) The status of each virtual MDIO node that is referenced by an Ethernet 32 * node is set to "okay". 33 * 34 * 2) The phy-handle property of each active Ethernet MAC node is set to the 35 * appropriate PHY node. 36 * 37 * 3) The "mux value" for each virtual MDIO node is set to the correct value, 38 * if necessary. Some virtual MDIO nodes do not have configurable mux 39 * values, so those values are hard-coded in the DTS. On the HYDRA board, 40 * the virtual MDIO node for the SGMII card needs to be updated. 41 * 42 * For all this to work, the device tree needs to have the following: 43 * 44 * 1) An alias for each PHY node that an Ethernet node could be routed to. 45 * 46 * 2) An alias for each real and virtual MDIO node that is disabled by default 47 * and might need to be enabled, and also might need to have its mux-value 48 * updated. 49 */ 50 51 #include <common.h> 52 #include <netdev.h> 53 #include <asm/fsl_serdes.h> 54 #include <fm_eth.h> 55 #include <fsl_mdio.h> 56 #include <malloc.h> 57 #include <fdt_support.h> 58 #include <asm/fsl_dtsec.h> 59 60 #include "../common/ngpixis.h" 61 #include "../common/fman.h" 62 63 #ifdef CONFIG_FMAN_ENET 64 65 #define BRDCFG1_EMI1_SEL_MASK 0x70 66 #define BRDCFG1_EMI1_SEL_SLOT1 0x10 67 #define BRDCFG1_EMI1_SEL_SLOT2 0x20 68 #define BRDCFG1_EMI1_SEL_SLOT5 0x30 69 #define BRDCFG1_EMI1_SEL_SLOT6 0x40 70 #define BRDCFG1_EMI1_SEL_SLOT7 0x50 71 #define BRDCFG1_EMI1_SEL_RGMII 0x00 72 #define BRDCFG1_EMI1_EN 0x08 73 #define BRDCFG1_EMI2_SEL_MASK 0x06 74 #define BRDCFG1_EMI2_SEL_SLOT1 0x00 75 #define BRDCFG1_EMI2_SEL_SLOT2 0x02 76 77 #define BRDCFG2_REG_GPIO_SEL 0x20 78 79 /* 80 * BRDCFG1 mask and value for each MAC 81 * 82 * This array contains the BRDCFG1 values (in mask/val format) that route the 83 * MDIO bus to a particular RGMII or SGMII PHY. 84 */ 85 struct { 86 u8 mask; 87 u8 val; 88 } mdio_mux[NUM_FM_PORTS]; 89 90 /* 91 * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means 92 * that the mapping must be determined dynamically, or that the lane maps to 93 * something other than a board slot 94 */ 95 static u8 lane_to_slot[] = { 96 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0 97 }; 98 99 /* 100 * Set the board muxing for a given MAC 101 * 102 * The MDIO layer calls this function every time it wants to talk to a PHY. 103 */ 104 void hydra_mux_mdio(u8 mask, u8 val) 105 { 106 clrsetbits_8(&pixis->brdcfg1, mask, val); 107 } 108 109 struct hydra_mdio { 110 u8 mask; 111 u8 val; 112 struct mii_dev *realbus; 113 }; 114 115 static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad, 116 int regnum) 117 { 118 struct hydra_mdio *priv = bus->priv; 119 120 hydra_mux_mdio(priv->mask, priv->val); 121 122 return priv->realbus->read(priv->realbus, addr, devad, regnum); 123 } 124 125 static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad, 126 int regnum, u16 value) 127 { 128 struct hydra_mdio *priv = bus->priv; 129 130 hydra_mux_mdio(priv->mask, priv->val); 131 132 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); 133 } 134 135 static int hydra_mdio_reset(struct mii_dev *bus) 136 { 137 struct hydra_mdio *priv = bus->priv; 138 139 return priv->realbus->reset(priv->realbus); 140 } 141 142 static void hydra_mdio_set_mux(char *name, u8 mask, u8 val) 143 { 144 struct mii_dev *bus = miiphy_get_dev_by_name(name); 145 struct hydra_mdio *priv = bus->priv; 146 147 priv->mask = mask; 148 priv->val = val; 149 } 150 151 static int hydra_mdio_init(char *realbusname, char *fakebusname) 152 { 153 struct hydra_mdio *hmdio; 154 struct mii_dev *bus = mdio_alloc(); 155 156 if (!bus) { 157 printf("Failed to allocate Hydra MDIO bus\n"); 158 return -1; 159 } 160 161 hmdio = malloc(sizeof(*hmdio)); 162 if (!hmdio) { 163 printf("Failed to allocate Hydra private data\n"); 164 free(bus); 165 return -1; 166 } 167 168 bus->read = hydra_mdio_read; 169 bus->write = hydra_mdio_write; 170 bus->reset = hydra_mdio_reset; 171 sprintf(bus->name, fakebusname); 172 173 hmdio->realbus = miiphy_get_dev_by_name(realbusname); 174 175 if (!hmdio->realbus) { 176 printf("No bus with name %s\n", realbusname); 177 free(bus); 178 free(hmdio); 179 return -1; 180 } 181 182 bus->priv = hmdio; 183 184 return mdio_register(bus); 185 } 186 187 /* 188 * Given an alias or a path for a node, set the mux value of that node. 189 * 190 * If 'alias' is not a valid alias, then it is treated as a full path to the 191 * node. No error checking is performed. 192 * 193 * This function is normally called to set the fsl,hydra-mdio-muxval property 194 * of a virtual MDIO node. 195 */ 196 static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux) 197 { 198 const char *path = fdt_get_alias(fdt, alias); 199 200 if (!path) 201 path = alias; 202 203 do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval", 204 &mux, sizeof(mux), 1); 205 } 206 207 /* 208 * Given the following ... 209 * 210 * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' 211 * compatible string and 'addr' physical address) 212 * 213 * 2) An Fman port 214 * 215 * ... update the phy-handle property of the Ethernet node to point to the 216 * right PHY. This assumes that we already know the PHY for each port. That 217 * information is stored in mdio_mux[]. 218 * 219 * The offset of the Fman Ethernet node is also passed in for convenience, but 220 * it is not used, and we recalculate the offset anyway. 221 * 222 * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. 223 * Inside the Fman, "ports" are things that connect to MACs. We only call them 224 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs 225 * and ports are the same thing. 226 * 227 * Note that this code would be cleaner if had a function called 228 * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[] 229 * array. That's because all we're doing is figuring out the PHY address for 230 * a given Fman MAC and writing it to the device tree. Well, we already did 231 * the hard work to figure that out in board_eth_init(), so it's silly to 232 * repeat that here. 233 */ 234 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, 235 enum fm_port port, int offset) 236 { 237 unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask; 238 char phy[16]; 239 240 if (port == FM1_10GEC1) { 241 /* XAUI */ 242 int lane = serdes_get_first_lane(XAUI_FM1); 243 if (lane >= 0) { 244 /* The XAUI PHY is identified by the slot */ 245 sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); 246 fdt_set_phy_handle(fdt, compat, addr, phy); 247 } 248 return; 249 } 250 251 if (mux == BRDCFG1_EMI1_SEL_RGMII) { 252 /* RGMII */ 253 /* The RGMII PHY is identified by the MAC connected to it */ 254 sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1); 255 fdt_set_phy_handle(fdt, compat, addr, phy); 256 } 257 258 /* If it's not RGMII or XGMII, it must be SGMII */ 259 if (mux) { 260 /* The SGMII PHY is identified by the MAC connected to it */ 261 sprintf(phy, "phy_sgmii_%x", 262 CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1)); 263 fdt_set_phy_handle(fdt, compat, addr, phy); 264 } 265 } 266 267 #define PIXIS_SW2_LANE_23_SEL 0x80 268 #define PIXIS_SW2_LANE_45_SEL 0x40 269 #define PIXIS_SW2_LANE_67_SEL_MASK 0x30 270 #define PIXIS_SW2_LANE_67_SEL_5 0x00 271 #define PIXIS_SW2_LANE_67_SEL_6 0x20 272 #define PIXIS_SW2_LANE_67_SEL_7 0x10 273 #define PIXIS_SW2_LANE_8_SEL 0x08 274 #define PIXIS_SW2_LANE_1617_SEL 0x04 275 276 /* 277 * Initialize the lane_to_slot[] array. 278 * 279 * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board 280 * slots is hard-coded. On the Hydra board, however, the mapping is controlled 281 * by board switch SW2, so the lane_to_slot[] array needs to be dynamically 282 * initialized. 283 */ 284 static void initialize_lane_to_slot(void) 285 { 286 u8 sw2 = in_8(&PIXIS_SW(2)); 287 288 lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; 289 lane_to_slot[3] = lane_to_slot[2]; 290 291 lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; 292 lane_to_slot[5] = lane_to_slot[4]; 293 294 switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { 295 case PIXIS_SW2_LANE_67_SEL_5: 296 lane_to_slot[6] = 5; 297 break; 298 case PIXIS_SW2_LANE_67_SEL_6: 299 lane_to_slot[6] = 6; 300 break; 301 case PIXIS_SW2_LANE_67_SEL_7: 302 lane_to_slot[6] = 7; 303 break; 304 } 305 lane_to_slot[7] = lane_to_slot[6]; 306 307 lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; 308 309 lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; 310 lane_to_slot[17] = lane_to_slot[16]; 311 } 312 313 #endif /* #ifdef CONFIG_FMAN_ENET */ 314 315 /* 316 * Configure the status for the virtual MDIO nodes 317 * 318 * Rather than create the virtual MDIO nodes from scratch for each active 319 * virtual MDIO, we expect the DTS to have the nodes defined already, and we 320 * only enable the ones that are actually active. 321 * 322 * We assume that the DTS already hard-codes the status for all the 323 * virtual MDIO nodes to "disabled", so all we need to do is enable the 324 * active ones. 325 * 326 * For SGMII, we also need to set the mux value in the node. 327 */ 328 void fdt_fixup_board_enet(void *fdt) 329 { 330 #ifdef CONFIG_FMAN_ENET 331 unsigned int i; 332 int lane; 333 334 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 335 int idx = i - FM1_DTSEC1; 336 337 switch (fm_info_get_enet_if(i)) { 338 case PHY_INTERFACE_MODE_SGMII: 339 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); 340 if (lane >= 0) { 341 fdt_status_okay_by_alias(fdt, "emi1_sgmii"); 342 /* Also set the MUX value */ 343 fdt_set_mdio_mux(fdt, "emi1_sgmii", 344 mdio_mux[i].val); 345 } 346 break; 347 case PHY_INTERFACE_MODE_RGMII: 348 fdt_status_okay_by_alias(fdt, "emi1_rgmii"); 349 break; 350 default: 351 break; 352 } 353 } 354 355 lane = serdes_get_first_lane(XAUI_FM1); 356 if (lane >= 0) 357 fdt_status_okay_by_alias(fdt, "emi2_xgmii"); 358 #endif 359 } 360 361 int board_eth_init(bd_t *bis) 362 { 363 #ifdef CONFIG_FMAN_ENET 364 struct fsl_pq_mdio_info dtsec_mdio_info; 365 struct tgec_mdio_info tgec_mdio_info; 366 unsigned int i, slot; 367 int lane; 368 369 printf("Initializing Fman\n"); 370 371 initialize_lane_to_slot(); 372 373 /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ 374 setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); 375 376 memset(mdio_mux, 0, sizeof(mdio_mux)); 377 378 dtsec_mdio_info.regs = 379 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; 380 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 381 382 /* Register the real 1G MDIO bus */ 383 fsl_pq_mdio_init(bis, &dtsec_mdio_info); 384 385 tgec_mdio_info.regs = 386 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; 387 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 388 389 /* Register the real 10G MDIO bus */ 390 fm_tgec_mdio_init(bis, &tgec_mdio_info); 391 392 /* Register the three virtual MDIO front-ends */ 393 hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO"); 394 hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO"); 395 396 /* 397 * Program the DTSEC PHY addresses assuming that they are all SGMII. 398 * For any DTSEC that's RGMII, we'll override its PHY address later. 399 * We assume that DTSEC5 is only used for RGMII. 400 */ 401 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); 402 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); 403 fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); 404 fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); 405 406 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 407 int idx = i - FM1_DTSEC1; 408 409 switch (fm_info_get_enet_if(i)) { 410 case PHY_INTERFACE_MODE_SGMII: 411 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); 412 if (lane < 0) 413 break; 414 slot = lane_to_slot[lane]; 415 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; 416 switch (slot) { 417 case 1: 418 /* Always DTSEC5 on Bank 3 */ 419 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | 420 BRDCFG1_EMI1_EN; 421 break; 422 case 2: 423 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | 424 BRDCFG1_EMI1_EN; 425 break; 426 case 5: 427 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | 428 BRDCFG1_EMI1_EN; 429 break; 430 case 6: 431 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | 432 BRDCFG1_EMI1_EN; 433 break; 434 case 7: 435 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | 436 BRDCFG1_EMI1_EN; 437 break; 438 }; 439 440 hydra_mdio_set_mux("HYDRA_SGMII_MDIO", 441 mdio_mux[i].mask, mdio_mux[i].val); 442 fm_info_set_mdio(i, 443 miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); 444 break; 445 case PHY_INTERFACE_MODE_RGMII: 446 /* 447 * If DTSEC4 is RGMII, then it's routed via via EC1 to 448 * the first on-board RGMII port. If DTSEC5 is RGMII, 449 * then it's routed via via EC2 to the second on-board 450 * RGMII port. The other DTSECs cannot be routed to 451 * RGMII. 452 */ 453 fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1); 454 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; 455 mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | 456 BRDCFG1_EMI1_EN; 457 hydra_mdio_set_mux("HYDRA_RGMII_MDIO", 458 mdio_mux[i].mask, mdio_mux[i].val); 459 fm_info_set_mdio(i, 460 miiphy_get_dev_by_name("HYDRA_RGMII_MDIO")); 461 break; 462 case PHY_INTERFACE_MODE_NONE: 463 fm_info_set_phy_address(i, 0); 464 break; 465 default: 466 printf("Fman1: DTSEC%u set to unknown interface %i\n", 467 idx + 1, fm_info_get_enet_if(i)); 468 fm_info_set_phy_address(i, 0); 469 break; 470 } 471 } 472 473 /* 474 * For 10G, we only support one XAUI card per Fman. If present, then we 475 * force its routing and never touch those bits again, which removes the 476 * need for Linux to do any muxing. This works because of the way 477 * BRDCFG1 is defined, but it's a bit hackish. 478 * 479 * The PHY address for the XAUI card depends on which slot it's in. The 480 * macros we use imply that the PHY address is based on which FM, but 481 * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, 482 * and FM2 could only use a XAUI in slot 4. On the Hydra board, we 483 * check the actual slot and just use the macros as-is, even though 484 * the P3041 and P5020 only have one Fman. 485 */ 486 lane = serdes_get_first_lane(XAUI_FM1); 487 if (lane >= 0) { 488 slot = lane_to_slot[lane]; 489 if (slot == 1) { 490 /* XAUI card is in slot 1 */ 491 clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, 492 BRDCFG1_EMI2_SEL_SLOT1); 493 fm_info_set_phy_address(FM1_10GEC1, 494 CONFIG_SYS_FM1_10GEC1_PHY_ADDR); 495 } else { 496 /* XAUI card is in slot 2 */ 497 clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, 498 BRDCFG1_EMI2_SEL_SLOT2); 499 fm_info_set_phy_address(FM1_10GEC1, 500 CONFIG_SYS_FM2_10GEC1_PHY_ADDR); 501 } 502 } 503 504 fm_info_set_mdio(FM1_10GEC1, 505 miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); 506 507 cpu_eth_init(bis); 508 #endif 509 510 return pci_eth_init(bis); 511 } 512