1cba46148STimur Tabi /* 2cba46148STimur Tabi * Copyright 2009-2011 Freescale Semiconductor, Inc. 3cba46148STimur Tabi * Author: Timur Tabi <timur@freescale.com> 4cba46148STimur Tabi * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6cba46148STimur Tabi */ 7cba46148STimur Tabi 8cba46148STimur Tabi /* 9cba46148STimur Tabi * This file handles the board muxing between the Fman Ethernet MACs and 10cba46148STimur Tabi * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference 11cba46148STimur Tabi * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are 12cba46148STimur Tabi * provided by the standard Freescale four-port SGMII riser card. The 10Gb 13cba46148STimur Tabi * XGMII PHY is provided via the XAUI riser card. Since there is only one 14cba46148STimur Tabi * Fman device on a P3041 and P5020, we only support one SGMII card and one 15cba46148STimur Tabi * RGMII card. 16cba46148STimur Tabi * 17cba46148STimur Tabi * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control 18cba46148STimur Tabi * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is 19cba46148STimur Tabi * always the same (0). The value for SGMII depends on which slot the riser is 20cba46148STimur Tabi * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, 21cba46148STimur Tabi * the value is based on which slot the XAUI is inserted in. 22cba46148STimur Tabi * 23cba46148STimur Tabi * The SERDES configuration is used to determine where the SGMII and XAUI cards 24cba46148STimur Tabi * exist, and also which Fman MACs are routed to which PHYs. So for a given 25cba46148STimur Tabi * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed 26cba46148STimur Tabi * to PHYs dynamically. 27cba46148STimur Tabi * 28cba46148STimur Tabi * 29cba46148STimur Tabi * This file also updates the device tree in three ways: 30cba46148STimur Tabi * 31cba46148STimur Tabi * 1) The status of each virtual MDIO node that is referenced by an Ethernet 32cba46148STimur Tabi * node is set to "okay". 33cba46148STimur Tabi * 34cba46148STimur Tabi * 2) The phy-handle property of each active Ethernet MAC node is set to the 35cba46148STimur Tabi * appropriate PHY node. 36cba46148STimur Tabi * 37cba46148STimur Tabi * 3) The "mux value" for each virtual MDIO node is set to the correct value, 38cba46148STimur Tabi * if necessary. Some virtual MDIO nodes do not have configurable mux 39cba46148STimur Tabi * values, so those values are hard-coded in the DTS. On the HYDRA board, 40cba46148STimur Tabi * the virtual MDIO node for the SGMII card needs to be updated. 41cba46148STimur Tabi * 42cba46148STimur Tabi * For all this to work, the device tree needs to have the following: 43cba46148STimur Tabi * 44cba46148STimur Tabi * 1) An alias for each PHY node that an Ethernet node could be routed to. 45cba46148STimur Tabi * 46cba46148STimur Tabi * 2) An alias for each real and virtual MDIO node that is disabled by default 47cba46148STimur Tabi * and might need to be enabled, and also might need to have its mux-value 48cba46148STimur Tabi * updated. 49cba46148STimur Tabi */ 50cba46148STimur Tabi 51cba46148STimur Tabi #include <common.h> 52cba46148STimur Tabi #include <netdev.h> 53cba46148STimur Tabi #include <asm/fsl_serdes.h> 54cba46148STimur Tabi #include <fm_eth.h> 55cba46148STimur Tabi #include <fsl_mdio.h> 56cba46148STimur Tabi #include <malloc.h> 572a523f52SShengzhou Liu #include <fdt_support.h> 58cba46148STimur Tabi #include <asm/fsl_dtsec.h> 59cba46148STimur Tabi 60cba46148STimur Tabi #include "../common/ngpixis.h" 61cba46148STimur Tabi #include "../common/fman.h" 62cba46148STimur Tabi 63cba46148STimur Tabi #ifdef CONFIG_FMAN_ENET 64cba46148STimur Tabi 65cba46148STimur Tabi #define BRDCFG1_EMI1_SEL_MASK 0x70 66cba46148STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT1 0x10 67cba46148STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT2 0x20 68cba46148STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT5 0x30 69cba46148STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT6 0x40 70cba46148STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT7 0x50 71cba46148STimur Tabi #define BRDCFG1_EMI1_SEL_RGMII 0x00 72cba46148STimur Tabi #define BRDCFG1_EMI1_EN 0x08 73cba46148STimur Tabi #define BRDCFG1_EMI2_SEL_MASK 0x06 74cba46148STimur Tabi #define BRDCFG1_EMI2_SEL_SLOT1 0x00 75cba46148STimur Tabi #define BRDCFG1_EMI2_SEL_SLOT2 0x02 76cba46148STimur Tabi 77cba46148STimur Tabi #define BRDCFG2_REG_GPIO_SEL 0x20 78cba46148STimur Tabi 79cba46148STimur Tabi /* 80cba46148STimur Tabi * BRDCFG1 mask and value for each MAC 81cba46148STimur Tabi * 82cba46148STimur Tabi * This array contains the BRDCFG1 values (in mask/val format) that route the 83cba46148STimur Tabi * MDIO bus to a particular RGMII or SGMII PHY. 84cba46148STimur Tabi */ 85cba46148STimur Tabi struct { 86cba46148STimur Tabi u8 mask; 87cba46148STimur Tabi u8 val; 88cba46148STimur Tabi } mdio_mux[NUM_FM_PORTS]; 89cba46148STimur Tabi 90cba46148STimur Tabi /* 91cba46148STimur Tabi * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means 92cba46148STimur Tabi * that the mapping must be determined dynamically, or that the lane maps to 93cba46148STimur Tabi * something other than a board slot 94cba46148STimur Tabi */ 95cba46148STimur Tabi static u8 lane_to_slot[] = { 96cba46148STimur Tabi 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0 97cba46148STimur Tabi }; 98cba46148STimur Tabi 99cba46148STimur Tabi /* 100cba46148STimur Tabi * Set the board muxing for a given MAC 101cba46148STimur Tabi * 102cba46148STimur Tabi * The MDIO layer calls this function every time it wants to talk to a PHY. 103cba46148STimur Tabi */ 104cba46148STimur Tabi void hydra_mux_mdio(u8 mask, u8 val) 105cba46148STimur Tabi { 106cba46148STimur Tabi clrsetbits_8(&pixis->brdcfg1, mask, val); 107cba46148STimur Tabi } 108cba46148STimur Tabi 109cba46148STimur Tabi struct hydra_mdio { 110cba46148STimur Tabi u8 mask; 111cba46148STimur Tabi u8 val; 112cba46148STimur Tabi struct mii_dev *realbus; 113cba46148STimur Tabi }; 114cba46148STimur Tabi 115cba46148STimur Tabi static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad, 116cba46148STimur Tabi int regnum) 117cba46148STimur Tabi { 118cba46148STimur Tabi struct hydra_mdio *priv = bus->priv; 119cba46148STimur Tabi 120cba46148STimur Tabi hydra_mux_mdio(priv->mask, priv->val); 121cba46148STimur Tabi 122cba46148STimur Tabi return priv->realbus->read(priv->realbus, addr, devad, regnum); 123cba46148STimur Tabi } 124cba46148STimur Tabi 125cba46148STimur Tabi static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad, 126cba46148STimur Tabi int regnum, u16 value) 127cba46148STimur Tabi { 128cba46148STimur Tabi struct hydra_mdio *priv = bus->priv; 129cba46148STimur Tabi 130cba46148STimur Tabi hydra_mux_mdio(priv->mask, priv->val); 131cba46148STimur Tabi 132cba46148STimur Tabi return priv->realbus->write(priv->realbus, addr, devad, regnum, value); 133cba46148STimur Tabi } 134cba46148STimur Tabi 135cba46148STimur Tabi static int hydra_mdio_reset(struct mii_dev *bus) 136cba46148STimur Tabi { 137cba46148STimur Tabi struct hydra_mdio *priv = bus->priv; 138cba46148STimur Tabi 139cba46148STimur Tabi return priv->realbus->reset(priv->realbus); 140cba46148STimur Tabi } 141cba46148STimur Tabi 142cba46148STimur Tabi static void hydra_mdio_set_mux(char *name, u8 mask, u8 val) 143cba46148STimur Tabi { 144cba46148STimur Tabi struct mii_dev *bus = miiphy_get_dev_by_name(name); 145cba46148STimur Tabi struct hydra_mdio *priv = bus->priv; 146cba46148STimur Tabi 147cba46148STimur Tabi priv->mask = mask; 148cba46148STimur Tabi priv->val = val; 149cba46148STimur Tabi } 150cba46148STimur Tabi 151cba46148STimur Tabi static int hydra_mdio_init(char *realbusname, char *fakebusname) 152cba46148STimur Tabi { 153cba46148STimur Tabi struct hydra_mdio *hmdio; 154cba46148STimur Tabi struct mii_dev *bus = mdio_alloc(); 155cba46148STimur Tabi 156cba46148STimur Tabi if (!bus) { 157cba46148STimur Tabi printf("Failed to allocate Hydra MDIO bus\n"); 158cba46148STimur Tabi return -1; 159cba46148STimur Tabi } 160cba46148STimur Tabi 161cba46148STimur Tabi hmdio = malloc(sizeof(*hmdio)); 162cba46148STimur Tabi if (!hmdio) { 163cba46148STimur Tabi printf("Failed to allocate Hydra private data\n"); 164cba46148STimur Tabi free(bus); 165cba46148STimur Tabi return -1; 166cba46148STimur Tabi } 167cba46148STimur Tabi 168cba46148STimur Tabi bus->read = hydra_mdio_read; 169cba46148STimur Tabi bus->write = hydra_mdio_write; 170cba46148STimur Tabi bus->reset = hydra_mdio_reset; 171cba46148STimur Tabi sprintf(bus->name, fakebusname); 172cba46148STimur Tabi 173cba46148STimur Tabi hmdio->realbus = miiphy_get_dev_by_name(realbusname); 174cba46148STimur Tabi 175cba46148STimur Tabi if (!hmdio->realbus) { 176cba46148STimur Tabi printf("No bus with name %s\n", realbusname); 177cba46148STimur Tabi free(bus); 178cba46148STimur Tabi free(hmdio); 179cba46148STimur Tabi return -1; 180cba46148STimur Tabi } 181cba46148STimur Tabi 182cba46148STimur Tabi bus->priv = hmdio; 183cba46148STimur Tabi 184cba46148STimur Tabi return mdio_register(bus); 185cba46148STimur Tabi } 186cba46148STimur Tabi 187cba46148STimur Tabi /* 188cba46148STimur Tabi * Given an alias or a path for a node, set the mux value of that node. 189cba46148STimur Tabi * 190cba46148STimur Tabi * If 'alias' is not a valid alias, then it is treated as a full path to the 191cba46148STimur Tabi * node. No error checking is performed. 192cba46148STimur Tabi * 193cba46148STimur Tabi * This function is normally called to set the fsl,hydra-mdio-muxval property 194cba46148STimur Tabi * of a virtual MDIO node. 195cba46148STimur Tabi */ 196cba46148STimur Tabi static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux) 197cba46148STimur Tabi { 198cba46148STimur Tabi const char *path = fdt_get_alias(fdt, alias); 199cba46148STimur Tabi 200cba46148STimur Tabi if (!path) 201cba46148STimur Tabi path = alias; 202cba46148STimur Tabi 203cba46148STimur Tabi do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval", 204cba46148STimur Tabi &mux, sizeof(mux), 1); 205cba46148STimur Tabi } 206cba46148STimur Tabi 207cba46148STimur Tabi /* 208cba46148STimur Tabi * Given the following ... 209cba46148STimur Tabi * 210cba46148STimur Tabi * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' 211cba46148STimur Tabi * compatible string and 'addr' physical address) 212cba46148STimur Tabi * 213cba46148STimur Tabi * 2) An Fman port 214cba46148STimur Tabi * 215cba46148STimur Tabi * ... update the phy-handle property of the Ethernet node to point to the 216cba46148STimur Tabi * right PHY. This assumes that we already know the PHY for each port. That 217cba46148STimur Tabi * information is stored in mdio_mux[]. 218cba46148STimur Tabi * 219cba46148STimur Tabi * The offset of the Fman Ethernet node is also passed in for convenience, but 220cba46148STimur Tabi * it is not used, and we recalculate the offset anyway. 221cba46148STimur Tabi * 222cba46148STimur Tabi * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. 223cba46148STimur Tabi * Inside the Fman, "ports" are things that connect to MACs. We only call them 224cba46148STimur Tabi * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs 225cba46148STimur Tabi * and ports are the same thing. 226cba46148STimur Tabi * 227cba46148STimur Tabi * Note that this code would be cleaner if had a function called 228cba46148STimur Tabi * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[] 229cba46148STimur Tabi * array. That's because all we're doing is figuring out the PHY address for 230cba46148STimur Tabi * a given Fman MAC and writing it to the device tree. Well, we already did 231cba46148STimur Tabi * the hard work to figure that out in board_eth_init(), so it's silly to 232cba46148STimur Tabi * repeat that here. 233cba46148STimur Tabi */ 234cba46148STimur Tabi void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, 235cba46148STimur Tabi enum fm_port port, int offset) 236cba46148STimur Tabi { 237cba46148STimur Tabi unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask; 238cba46148STimur Tabi char phy[16]; 239cba46148STimur Tabi 240cba46148STimur Tabi if (port == FM1_10GEC1) { 241cba46148STimur Tabi /* XAUI */ 242cba46148STimur Tabi int lane = serdes_get_first_lane(XAUI_FM1); 243cba46148STimur Tabi if (lane >= 0) { 244cba46148STimur Tabi /* The XAUI PHY is identified by the slot */ 245cba46148STimur Tabi sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); 246cba46148STimur Tabi fdt_set_phy_handle(fdt, compat, addr, phy); 247cba46148STimur Tabi } 248cba46148STimur Tabi return; 249cba46148STimur Tabi } 250cba46148STimur Tabi 251cba46148STimur Tabi if (mux == BRDCFG1_EMI1_SEL_RGMII) { 252cba46148STimur Tabi /* RGMII */ 253cba46148STimur Tabi /* The RGMII PHY is identified by the MAC connected to it */ 254cba46148STimur Tabi sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1); 255cba46148STimur Tabi fdt_set_phy_handle(fdt, compat, addr, phy); 256cba46148STimur Tabi } 257cba46148STimur Tabi 258cba46148STimur Tabi /* If it's not RGMII or XGMII, it must be SGMII */ 259cba46148STimur Tabi if (mux) { 260cba46148STimur Tabi /* The SGMII PHY is identified by the MAC connected to it */ 261cba46148STimur Tabi sprintf(phy, "phy_sgmii_%x", 262cba46148STimur Tabi CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1)); 263cba46148STimur Tabi fdt_set_phy_handle(fdt, compat, addr, phy); 264cba46148STimur Tabi } 265cba46148STimur Tabi } 266cba46148STimur Tabi 267cba46148STimur Tabi #define PIXIS_SW2_LANE_23_SEL 0x80 268cba46148STimur Tabi #define PIXIS_SW2_LANE_45_SEL 0x40 269cba46148STimur Tabi #define PIXIS_SW2_LANE_67_SEL_MASK 0x30 270cba46148STimur Tabi #define PIXIS_SW2_LANE_67_SEL_5 0x00 271cba46148STimur Tabi #define PIXIS_SW2_LANE_67_SEL_6 0x20 272cba46148STimur Tabi #define PIXIS_SW2_LANE_67_SEL_7 0x10 273cba46148STimur Tabi #define PIXIS_SW2_LANE_8_SEL 0x08 274cba46148STimur Tabi #define PIXIS_SW2_LANE_1617_SEL 0x04 275cba46148STimur Tabi 276cba46148STimur Tabi /* 277cba46148STimur Tabi * Initialize the lane_to_slot[] array. 278cba46148STimur Tabi * 279cba46148STimur Tabi * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board 280cba46148STimur Tabi * slots is hard-coded. On the Hydra board, however, the mapping is controlled 281cba46148STimur Tabi * by board switch SW2, so the lane_to_slot[] array needs to be dynamically 282cba46148STimur Tabi * initialized. 283cba46148STimur Tabi */ 284cba46148STimur Tabi static void initialize_lane_to_slot(void) 285cba46148STimur Tabi { 286cba46148STimur Tabi u8 sw2 = in_8(&PIXIS_SW(2)); 287cba46148STimur Tabi 288cba46148STimur Tabi lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; 289cba46148STimur Tabi lane_to_slot[3] = lane_to_slot[2]; 290cba46148STimur Tabi 291cba46148STimur Tabi lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; 292cba46148STimur Tabi lane_to_slot[5] = lane_to_slot[4]; 293cba46148STimur Tabi 294cba46148STimur Tabi switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { 295cba46148STimur Tabi case PIXIS_SW2_LANE_67_SEL_5: 296cba46148STimur Tabi lane_to_slot[6] = 5; 297cba46148STimur Tabi break; 298cba46148STimur Tabi case PIXIS_SW2_LANE_67_SEL_6: 299cba46148STimur Tabi lane_to_slot[6] = 6; 300cba46148STimur Tabi break; 301cba46148STimur Tabi case PIXIS_SW2_LANE_67_SEL_7: 302cba46148STimur Tabi lane_to_slot[6] = 7; 303cba46148STimur Tabi break; 304cba46148STimur Tabi } 305cba46148STimur Tabi lane_to_slot[7] = lane_to_slot[6]; 306cba46148STimur Tabi 307cba46148STimur Tabi lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; 308cba46148STimur Tabi 309cba46148STimur Tabi lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; 310cba46148STimur Tabi lane_to_slot[17] = lane_to_slot[16]; 311cba46148STimur Tabi } 312cba46148STimur Tabi 313cba46148STimur Tabi #endif /* #ifdef CONFIG_FMAN_ENET */ 314cba46148STimur Tabi 315cba46148STimur Tabi /* 316cba46148STimur Tabi * Configure the status for the virtual MDIO nodes 317cba46148STimur Tabi * 318cba46148STimur Tabi * Rather than create the virtual MDIO nodes from scratch for each active 319cba46148STimur Tabi * virtual MDIO, we expect the DTS to have the nodes defined already, and we 320cba46148STimur Tabi * only enable the ones that are actually active. 321cba46148STimur Tabi * 322cba46148STimur Tabi * We assume that the DTS already hard-codes the status for all the 323cba46148STimur Tabi * virtual MDIO nodes to "disabled", so all we need to do is enable the 324cba46148STimur Tabi * active ones. 325cba46148STimur Tabi * 326cba46148STimur Tabi * For SGMII, we also need to set the mux value in the node. 327cba46148STimur Tabi */ 328cba46148STimur Tabi void fdt_fixup_board_enet(void *fdt) 329cba46148STimur Tabi { 330cba46148STimur Tabi #ifdef CONFIG_FMAN_ENET 331cba46148STimur Tabi unsigned int i; 332cba46148STimur Tabi int lane; 333cba46148STimur Tabi 334cba46148STimur Tabi for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 335cba46148STimur Tabi int idx = i - FM1_DTSEC1; 336cba46148STimur Tabi 337cba46148STimur Tabi switch (fm_info_get_enet_if(i)) { 338cba46148STimur Tabi case PHY_INTERFACE_MODE_SGMII: 339cba46148STimur Tabi lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); 340cba46148STimur Tabi if (lane >= 0) { 3412a523f52SShengzhou Liu fdt_status_okay_by_alias(fdt, "emi1_sgmii"); 342cba46148STimur Tabi /* Also set the MUX value */ 343cba46148STimur Tabi fdt_set_mdio_mux(fdt, "emi1_sgmii", 344cba46148STimur Tabi mdio_mux[i].val); 345cba46148STimur Tabi } 346cba46148STimur Tabi break; 347cba46148STimur Tabi case PHY_INTERFACE_MODE_RGMII: 3482a523f52SShengzhou Liu fdt_status_okay_by_alias(fdt, "emi1_rgmii"); 349cba46148STimur Tabi break; 350cba46148STimur Tabi default: 351cba46148STimur Tabi break; 352cba46148STimur Tabi } 353cba46148STimur Tabi } 354cba46148STimur Tabi 355cba46148STimur Tabi lane = serdes_get_first_lane(XAUI_FM1); 356cba46148STimur Tabi if (lane >= 0) 3572a523f52SShengzhou Liu fdt_status_okay_by_alias(fdt, "emi2_xgmii"); 358cba46148STimur Tabi #endif 359cba46148STimur Tabi } 360cba46148STimur Tabi 361cba46148STimur Tabi int board_eth_init(bd_t *bis) 362cba46148STimur Tabi { 363cba46148STimur Tabi #ifdef CONFIG_FMAN_ENET 364cba46148STimur Tabi struct fsl_pq_mdio_info dtsec_mdio_info; 365cba46148STimur Tabi struct tgec_mdio_info tgec_mdio_info; 366cba46148STimur Tabi unsigned int i, slot; 367cba46148STimur Tabi int lane; 368cba46148STimur Tabi 369cba46148STimur Tabi printf("Initializing Fman\n"); 370cba46148STimur Tabi 371cba46148STimur Tabi initialize_lane_to_slot(); 372cba46148STimur Tabi 373cba46148STimur Tabi /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ 374cba46148STimur Tabi setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); 375cba46148STimur Tabi 376cba46148STimur Tabi memset(mdio_mux, 0, sizeof(mdio_mux)); 377cba46148STimur Tabi 378cba46148STimur Tabi dtsec_mdio_info.regs = 379cba46148STimur Tabi (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; 380cba46148STimur Tabi dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 381cba46148STimur Tabi 382cba46148STimur Tabi /* Register the real 1G MDIO bus */ 383cba46148STimur Tabi fsl_pq_mdio_init(bis, &dtsec_mdio_info); 384cba46148STimur Tabi 385cba46148STimur Tabi tgec_mdio_info.regs = 386cba46148STimur Tabi (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; 387cba46148STimur Tabi tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 388cba46148STimur Tabi 389cba46148STimur Tabi /* Register the real 10G MDIO bus */ 390cba46148STimur Tabi fm_tgec_mdio_init(bis, &tgec_mdio_info); 391cba46148STimur Tabi 392cba46148STimur Tabi /* Register the three virtual MDIO front-ends */ 393cba46148STimur Tabi hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO"); 394cba46148STimur Tabi hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO"); 395cba46148STimur Tabi 396cba46148STimur Tabi /* 397cba46148STimur Tabi * Program the DTSEC PHY addresses assuming that they are all SGMII. 398cba46148STimur Tabi * For any DTSEC that's RGMII, we'll override its PHY address later. 399cba46148STimur Tabi * We assume that DTSEC5 is only used for RGMII. 400cba46148STimur Tabi */ 401cba46148STimur Tabi fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); 402cba46148STimur Tabi fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); 403cba46148STimur Tabi fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); 404cba46148STimur Tabi fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); 405cba46148STimur Tabi 406cba46148STimur Tabi for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 407cba46148STimur Tabi int idx = i - FM1_DTSEC1; 408cba46148STimur Tabi 409cba46148STimur Tabi switch (fm_info_get_enet_if(i)) { 410cba46148STimur Tabi case PHY_INTERFACE_MODE_SGMII: 411cba46148STimur Tabi lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); 412cba46148STimur Tabi if (lane < 0) 413cba46148STimur Tabi break; 414cba46148STimur Tabi slot = lane_to_slot[lane]; 415cba46148STimur Tabi mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; 416cba46148STimur Tabi switch (slot) { 417cba46148STimur Tabi case 1: 418cba46148STimur Tabi /* Always DTSEC5 on Bank 3 */ 419cba46148STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | 420cba46148STimur Tabi BRDCFG1_EMI1_EN; 421cba46148STimur Tabi break; 422cba46148STimur Tabi case 2: 423cba46148STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | 424cba46148STimur Tabi BRDCFG1_EMI1_EN; 425cba46148STimur Tabi break; 426cba46148STimur Tabi case 5: 427cba46148STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | 428cba46148STimur Tabi BRDCFG1_EMI1_EN; 429cba46148STimur Tabi break; 430cba46148STimur Tabi case 6: 431cba46148STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | 432cba46148STimur Tabi BRDCFG1_EMI1_EN; 433cba46148STimur Tabi break; 434cba46148STimur Tabi case 7: 435cba46148STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | 436cba46148STimur Tabi BRDCFG1_EMI1_EN; 437cba46148STimur Tabi break; 438cba46148STimur Tabi }; 439cba46148STimur Tabi 440cba46148STimur Tabi hydra_mdio_set_mux("HYDRA_SGMII_MDIO", 441cba46148STimur Tabi mdio_mux[i].mask, mdio_mux[i].val); 442cba46148STimur Tabi fm_info_set_mdio(i, 443cba46148STimur Tabi miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); 444cba46148STimur Tabi break; 445cba46148STimur Tabi case PHY_INTERFACE_MODE_RGMII: 446cba46148STimur Tabi /* 447cba46148STimur Tabi * If DTSEC4 is RGMII, then it's routed via via EC1 to 448cba46148STimur Tabi * the first on-board RGMII port. If DTSEC5 is RGMII, 449cba46148STimur Tabi * then it's routed via via EC2 to the second on-board 450cba46148STimur Tabi * RGMII port. The other DTSECs cannot be routed to 451cba46148STimur Tabi * RGMII. 452cba46148STimur Tabi */ 453cba46148STimur Tabi fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1); 454cba46148STimur Tabi mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; 455cba46148STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | 456cba46148STimur Tabi BRDCFG1_EMI1_EN; 457cba46148STimur Tabi hydra_mdio_set_mux("HYDRA_RGMII_MDIO", 458cba46148STimur Tabi mdio_mux[i].mask, mdio_mux[i].val); 459cba46148STimur Tabi fm_info_set_mdio(i, 460cba46148STimur Tabi miiphy_get_dev_by_name("HYDRA_RGMII_MDIO")); 461cba46148STimur Tabi break; 462cba46148STimur Tabi case PHY_INTERFACE_MODE_NONE: 463cba46148STimur Tabi fm_info_set_phy_address(i, 0); 464cba46148STimur Tabi break; 465cba46148STimur Tabi default: 466cba46148STimur Tabi printf("Fman1: DTSEC%u set to unknown interface %i\n", 467cba46148STimur Tabi idx + 1, fm_info_get_enet_if(i)); 468cba46148STimur Tabi fm_info_set_phy_address(i, 0); 469cba46148STimur Tabi break; 470cba46148STimur Tabi } 471cba46148STimur Tabi } 472cba46148STimur Tabi 473cba46148STimur Tabi /* 474cba46148STimur Tabi * For 10G, we only support one XAUI card per Fman. If present, then we 475cba46148STimur Tabi * force its routing and never touch those bits again, which removes the 476cba46148STimur Tabi * need for Linux to do any muxing. This works because of the way 477cba46148STimur Tabi * BRDCFG1 is defined, but it's a bit hackish. 478cba46148STimur Tabi * 479cba46148STimur Tabi * The PHY address for the XAUI card depends on which slot it's in. The 480cba46148STimur Tabi * macros we use imply that the PHY address is based on which FM, but 481cba46148STimur Tabi * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, 482cba46148STimur Tabi * and FM2 could only use a XAUI in slot 4. On the Hydra board, we 483cba46148STimur Tabi * check the actual slot and just use the macros as-is, even though 484cba46148STimur Tabi * the P3041 and P5020 only have one Fman. 485cba46148STimur Tabi */ 486cba46148STimur Tabi lane = serdes_get_first_lane(XAUI_FM1); 487cba46148STimur Tabi if (lane >= 0) { 488cba46148STimur Tabi slot = lane_to_slot[lane]; 489cba46148STimur Tabi if (slot == 1) { 490cba46148STimur Tabi /* XAUI card is in slot 1 */ 491cba46148STimur Tabi clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, 492cba46148STimur Tabi BRDCFG1_EMI2_SEL_SLOT1); 493cba46148STimur Tabi fm_info_set_phy_address(FM1_10GEC1, 494cba46148STimur Tabi CONFIG_SYS_FM1_10GEC1_PHY_ADDR); 495cba46148STimur Tabi } else { 496cba46148STimur Tabi /* XAUI card is in slot 2 */ 497cba46148STimur Tabi clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, 498cba46148STimur Tabi BRDCFG1_EMI2_SEL_SLOT2); 499cba46148STimur Tabi fm_info_set_phy_address(FM1_10GEC1, 500cba46148STimur Tabi CONFIG_SYS_FM2_10GEC1_PHY_ADDR); 501cba46148STimur Tabi } 502cba46148STimur Tabi } 503cba46148STimur Tabi 504cba46148STimur Tabi fm_info_set_mdio(FM1_10GEC1, 505cba46148STimur Tabi miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); 506cba46148STimur Tabi 507cba46148STimur Tabi cpu_eth_init(bis); 508cba46148STimur Tabi #endif 509cba46148STimur Tabi 510cba46148STimur Tabi return pci_eth_init(bis); 511cba46148STimur Tabi } 512