1 /*
2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8 
9 #include <common.h>
10 #include <i2c.h>
11 #include <hwconfig.h>
12 #include <asm/mmu.h>
13 #include <asm/fsl_ddr_sdram.h>
14 #include <asm/fsl_ddr_dimm_params.h>
15 #include <asm/fsl_law.h>
16 
17 DECLARE_GLOBAL_DATA_PTR;
18 
19 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
20 				   unsigned int ctrl_num);
21 
22 
23 /*
24  * Fixed sdram init -- doesn't use serial presence detect.
25  */
26 extern fixed_ddr_parm_t fixed_ddr_parm_0[];
27 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
28 extern fixed_ddr_parm_t fixed_ddr_parm_1[];
29 #endif
30 
31 phys_size_t fixed_sdram(void)
32 {
33 	int i;
34 	sys_info_t sysinfo;
35 	char buf[32];
36 	fsl_ddr_cfg_regs_t ddr_cfg_regs;
37 	phys_size_t ddr_size;
38 	unsigned int lawbar1_target_id;
39 
40 	get_sys_info(&sysinfo);
41 	printf("Configuring DDR for %s MT/s data rate\n",
42 				strmhz(buf, sysinfo.freqDDRBus));
43 
44 	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
45 		if ((sysinfo.freqDDRBus > fixed_ddr_parm_0[i].min_freq) &&
46 		   (sysinfo.freqDDRBus <= fixed_ddr_parm_0[i].max_freq)) {
47 			memcpy(&ddr_cfg_regs,
48 				fixed_ddr_parm_0[i].ddr_settings,
49 				sizeof(ddr_cfg_regs));
50 			break;
51 		}
52 	}
53 
54 	if (fixed_ddr_parm_0[i].max_freq == 0)
55 		panic("Unsupported DDR data rate %s MT/s data rate\n",
56 			strmhz(buf, sysinfo.freqDDRBus));
57 
58 	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
59 	ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
60 	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
61 
62 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
63 	memcpy(&ddr_cfg_regs,
64 		fixed_ddr_parm_1[i].ddr_settings,
65 		sizeof(ddr_cfg_regs));
66 	ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
67 	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
68 #endif
69 
70 	/*
71 	 * setup laws for DDR. If not interleaving, presuming half memory on
72 	 * DDR1 and the other half on DDR2
73 	 */
74 	if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
75 		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
76 				 ddr_size,
77 				 LAW_TRGT_IF_DDR_INTRLV) < 0) {
78 			printf("ERROR setting Local Access Windows for DDR\n");
79 			return 0;
80 		}
81 	} else {
82 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
83 		/* We require both controllers have identical DIMMs */
84 		lawbar1_target_id = LAW_TRGT_IF_DDR_1;
85 		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
86 				 ddr_size / 2,
87 				 lawbar1_target_id) < 0) {
88 			printf("ERROR setting Local Access Windows for DDR\n");
89 			return 0;
90 		}
91 		lawbar1_target_id = LAW_TRGT_IF_DDR_2;
92 		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
93 				 ddr_size / 2,
94 				 lawbar1_target_id) < 0) {
95 			printf("ERROR setting Local Access Windows for DDR\n");
96 			return 0;
97 		}
98 #else
99 		lawbar1_target_id = LAW_TRGT_IF_DDR_1;
100 		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
101 				 ddr_size,
102 				 lawbar1_target_id) < 0) {
103 			printf("ERROR setting Local Access Windows for DDR\n");
104 			return 0;
105 		}
106 #endif
107 	}
108 	return ddr_size;
109 }
110 
111 static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
112 {
113 	int ret;
114 
115 	ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
116 	if (ret) {
117 		debug("DDR: failed to read SPD from address %u\n", i2c_address);
118 		memset(spd, 0, sizeof(ddr3_spd_eeprom_t));
119 	}
120 }
121 
122 unsigned int fsl_ddr_get_mem_data_rate(void)
123 {
124 	return get_ddr_freq(0);
125 }
126 
127 void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
128 		      unsigned int ctrl_num)
129 {
130 	unsigned int i;
131 	unsigned int i2c_address = 0;
132 
133 	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
134 		if (ctrl_num == 0 && i == 0)
135 			i2c_address = SPD_EEPROM_ADDRESS1;
136 		else if (ctrl_num == 1 && i == 0)
137 			i2c_address = SPD_EEPROM_ADDRESS2;
138 
139 		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
140 	}
141 }
142 
143 typedef struct {
144 	u32 datarate_mhz_low;
145 	u32 datarate_mhz_high;
146 	u32 n_ranks;
147 	u32 clk_adjust;
148 	u32 wrlvl_start;
149 	u32 cpo;
150 	u32 write_data_delay;
151 	u32 force_2T;
152 } board_specific_parameters_t;
153 
154 /* ranges for parameters:
155  *  wr_data_delay = 0-6
156  *  clk adjust = 0-8
157  *  cpo 2-0x1E (30)
158  */
159 
160 
161 /* XXX: these values need to be checked for all interleaving modes.  */
162 /* XXX: No reliable dual-rank 800 MHz setting has been found.  It may
163  *      seem reliable, but errors will appear when memory intensive
164  *      program is run. */
165 /* XXX: Single rank at 800 MHz is OK.  */
166 const board_specific_parameters_t board_specific_parameters[][30] = {
167 	{
168 	/*
169 	 * memory controller 0
170 	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
171 	 * mhz| mhz|ranks|adjst| start | delay|
172 	 */
173 		{  0, 333,    4,    5,     7,   0xff,    2,  0},
174 		{334, 400,    4,    5,     7,   0xff,    2,  0},
175 		{401, 549,    4,    5,     7,   0xff,    2,  0},
176 		{550, 680,    4,    5,     7,   0xff,    2,  0},
177 		{681, 850,    4,    5,     7,   0xff,    2,  0},
178 		{851, 1050,   4,    5,     7,   0xff,    2,  0},
179 		{1051, 1250,  4,    5,     8,   0xff,    2,  0},
180 		{1251, 1350,  4,    5,     9,   0xff,    2,  0},
181 		{  0, 333,    2,    5,     7,   0xff,    2,  0},
182 		{334, 400,    2,    5,     7,   0xff,    2,  0},
183 		{401, 549,    2,    5,     7,   0xff,    2,  0},
184 		{550, 680,    2,    5,     7,   0xff,    2,  0},
185 		{681, 850,    2,    5,     7,   0xff,    2,  0},
186 		{851, 1050,   2,    5,     7,   0xff,    2,  0},
187 		{1051, 1250,  2,    5,     7,   0xff,    2,  0},
188 		{1251, 1350,  2,    5,     7,   0xff,    2,  0},
189 		{  0, 333,    1,    5,     7,   0xff,    2,  0},
190 		{334, 400,    1,    5,     7,   0xff,    2,  0},
191 		{401, 549,    1,    5,     7,   0xff,    2,  0},
192 		{550, 680,    1,    5,     7,   0xff,    2,  0},
193 		{681, 850,    1,    5,     7,   0xff,    2,  0}
194 	},
195 
196 	{
197 	/*
198 	 * memory controller 1
199 	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
200 	 * mhz| mhz|ranks|adjst| start | delay|
201 	 */
202 		{  0, 333,    4,    5,     7,   0xff,    2,  0},
203 		{334, 400,    4,    5,     7,   0xff,    2,  0},
204 		{401, 549,    4,    5,     7,   0xff,    2,  0},
205 		{550, 680,    4,    5,     7,   0xff,    2,  0},
206 		{681, 850,    4,    5,     7,   0xff,    2,  0},
207 		{851, 1050,   4,    5,     7,   0xff,    2,  0},
208 		{1051, 1250,  4,    5,     8,   0xff,    2,  0},
209 		{1251, 1350,  4,    5,     9,   0xff,    2,  0},
210 		{  0, 333,    2,    5,     7,   0xff,    2,  0},
211 		{334, 400,    2,    5,     7,   0xff,    2,  0},
212 		{401, 549,    2,    5,     7,   0xff,    2,  0},
213 		{550, 680,    2,    5,     7,   0xff,    2,  0},
214 		{681, 850,    2,    5,     7,   0xff,    2,  0},
215 		{851, 1050,   2,    5,     7,   0xff,    2,  0},
216 		{1051, 1250,  2,    5,     7,   0xff,    2,  0},
217 		{1251, 1350,  2,    5,     7,   0xff,    2,  0},
218 		{  0, 333,    1,    5,     7,   0xff,    2,  0},
219 		{334, 400,    1,    5,     7,   0xff,    2,  0},
220 		{401, 549,    1,    5,     7,   0xff,    2,  0},
221 		{550, 680,    1,    5,     7,   0xff,    2,  0},
222 		{681, 850,    1,    5,     7,   0xff,    2,  0}
223 	}
224 };
225 
226 void fsl_ddr_board_options(memctl_options_t *popts,
227 				dimm_params_t *pdimm,
228 				unsigned int ctrl_num)
229 {
230 	const board_specific_parameters_t *pbsp =
231 				&(board_specific_parameters[ctrl_num][0]);
232 	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
233 				sizeof(board_specific_parameters[0][0]);
234 	u32 i;
235 	ulong ddr_freq;
236 
237 	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
238 	 * freqency and n_banks specified in board_specific_parameters table.
239 	 */
240 	ddr_freq = get_ddr_freq(0) / 1000000;
241 	for (i = 0; i < num_params; i++) {
242 		if (ddr_freq >= pbsp->datarate_mhz_low &&
243 			ddr_freq <= pbsp->datarate_mhz_high &&
244 			pdimm[0].n_ranks == pbsp->n_ranks) {
245 			popts->cpo_override = pbsp->cpo;
246 			popts->write_data_delay = pbsp->write_data_delay;
247 			popts->clk_adjust = pbsp->clk_adjust;
248 			popts->wrlvl_start = pbsp->wrlvl_start;
249 			popts->twoT_en = pbsp->force_2T;
250 		}
251 		pbsp++;
252 	}
253 
254 	/*
255 	 * Factors to consider for half-strength driver enable:
256 	 *	- number of DIMMs installed
257 	 */
258 	popts->half_strength_driver_enable = 0;
259 	/*
260 	 * Write leveling override
261 	 */
262 	popts->wrlvl_override = 1;
263 	popts->wrlvl_sample = 0xf;
264 
265 	/*
266 	 * Rtt and Rtt_WR override
267 	 */
268 	popts->rtt_override = 0;
269 
270 	/* Enable ZQ calibration */
271 	popts->zq_en = 1;
272 
273 	/* DHC_EN =1, ODT = 60 Ohm */
274 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
275 
276 	/* override SPD values. rcw_2 should vary at differnt speed */
277 	if (pdimm[0].n_ranks == 4) {
278 		popts->rcw_override = 1;
279 		popts->rcw_1 = 0x000a5a00;
280 		if (ddr_freq <= 800)
281 			popts->rcw_2 = 0x00000000;
282 		else if (ddr_freq <= 1066)
283 			popts->rcw_2 = 0x00100000;
284 		else if (ddr_freq <= 1333)
285 			popts->rcw_2 = 0x00200000;
286 		else
287 			popts->rcw_2 = 0x00300000;
288 	}
289 }
290 
291 phys_size_t initdram(int board_type)
292 {
293 	phys_size_t dram_size;
294 
295 	puts("Initializing....");
296 
297 	if (fsl_use_spd()) {
298 		puts("using SPD\n");
299 		dram_size = fsl_ddr_sdram();
300 	} else {
301 		puts("using fixed parameters\n");
302 		dram_size = fixed_sdram();
303 	}
304 
305 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
306 	dram_size *= 0x100000;
307 
308 	puts("    DDR: ");
309 	return dram_size;
310 }
311