1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #include <common.h> 10 #include <i2c.h> 11 #include <hwconfig.h> 12 #include <asm/mmu.h> 13 #include <asm/fsl_ddr_sdram.h> 14 #include <asm/fsl_ddr_dimm_params.h> 15 #include <asm/fsl_law.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 20 /* 21 * Fixed sdram init -- doesn't use serial presence detect. 22 */ 23 extern fixed_ddr_parm_t fixed_ddr_parm_0[]; 24 #if (CONFIG_NUM_DDR_CONTROLLERS == 2) 25 extern fixed_ddr_parm_t fixed_ddr_parm_1[]; 26 #endif 27 28 phys_size_t fixed_sdram(void) 29 { 30 int i; 31 char buf[32]; 32 fsl_ddr_cfg_regs_t ddr_cfg_regs; 33 phys_size_t ddr_size; 34 unsigned int lawbar1_target_id; 35 ulong ddr_freq, ddr_freq_mhz; 36 37 ddr_freq = get_ddr_freq(0); 38 ddr_freq_mhz = ddr_freq / 1000000; 39 40 printf("Configuring DDR for %s MT/s data rate\n", 41 strmhz(buf, ddr_freq)); 42 43 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { 44 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && 45 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { 46 memcpy(&ddr_cfg_regs, 47 fixed_ddr_parm_0[i].ddr_settings, 48 sizeof(ddr_cfg_regs)); 49 break; 50 } 51 } 52 53 if (fixed_ddr_parm_0[i].max_freq == 0) 54 panic("Unsupported DDR data rate %s MT/s data rate\n", 55 strmhz(buf, ddr_freq)); 56 57 ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 58 ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; 59 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); 60 61 #if (CONFIG_NUM_DDR_CONTROLLERS == 2) 62 memcpy(&ddr_cfg_regs, 63 fixed_ddr_parm_1[i].ddr_settings, 64 sizeof(ddr_cfg_regs)); 65 ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; 66 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1); 67 #endif 68 69 /* 70 * setup laws for DDR. If not interleaving, presuming half memory on 71 * DDR1 and the other half on DDR2 72 */ 73 if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) { 74 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, 75 ddr_size, 76 LAW_TRGT_IF_DDR_INTRLV) < 0) { 77 printf("ERROR setting Local Access Windows for DDR\n"); 78 return 0; 79 } 80 } else { 81 #if (CONFIG_NUM_DDR_CONTROLLERS == 2) 82 /* We require both controllers have identical DIMMs */ 83 lawbar1_target_id = LAW_TRGT_IF_DDR_1; 84 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, 85 ddr_size / 2, 86 lawbar1_target_id) < 0) { 87 printf("ERROR setting Local Access Windows for DDR\n"); 88 return 0; 89 } 90 lawbar1_target_id = LAW_TRGT_IF_DDR_2; 91 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2, 92 ddr_size / 2, 93 lawbar1_target_id) < 0) { 94 printf("ERROR setting Local Access Windows for DDR\n"); 95 return 0; 96 } 97 #else 98 lawbar1_target_id = LAW_TRGT_IF_DDR_1; 99 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, 100 ddr_size, 101 lawbar1_target_id) < 0) { 102 printf("ERROR setting Local Access Windows for DDR\n"); 103 return 0; 104 } 105 #endif 106 } 107 return ddr_size; 108 } 109 110 struct board_specific_parameters { 111 u32 n_ranks; 112 u32 datarate_mhz_high; 113 u32 clk_adjust; 114 u32 wrlvl_start; 115 u32 cpo; 116 u32 write_data_delay; 117 u32 force_2T; 118 }; 119 120 /* 121 * This table contains all valid speeds we want to override with board 122 * specific parameters. datarate_mhz_high values need to be in ascending order 123 * for each n_ranks group. 124 */ 125 static const struct board_specific_parameters udimm0[] = { 126 /* 127 * memory controller 0 128 * num| hi| clk| wrlvl | cpo |wrdata|2T 129 * ranks| mhz|adjst| start | |delay | 130 */ 131 {4, 850, 4, 6, 0xff, 2, 0}, 132 {4, 950, 5, 7, 0xff, 2, 0}, 133 {4, 1050, 5, 8, 0xff, 2, 0}, 134 {4, 1250, 5, 10, 0xff, 2, 0}, 135 {4, 1350, 5, 11, 0xff, 2, 0}, 136 {4, 1666, 5, 12, 0xff, 2, 0}, 137 {2, 850, 5, 6, 0xff, 2, 0}, 138 {2, 1050, 5, 7, 0xff, 2, 0}, 139 {2, 1250, 4, 6, 0xff, 2, 0}, 140 {2, 1350, 5, 7, 0xff, 2, 0}, 141 {2, 1666, 5, 8, 0xff, 2, 0}, 142 {1, 850, 4, 5, 0xff, 2, 0}, 143 {1, 950, 4, 7, 0xff, 2, 0}, 144 {1, 1666, 4, 8, 0xff, 2, 0}, 145 {} 146 }; 147 148 /* 149 * The two slots have slightly different timing. The center values are good 150 * for both slots. We use identical speed tables for them. In future use, if 151 * DIMMs have fewer center values that require two separated tables, copy the 152 * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start. 153 */ 154 static const struct board_specific_parameters *udimms[] = { 155 udimm0, 156 udimm0, 157 }; 158 159 static const struct board_specific_parameters rdimm0[] = { 160 /* 161 * memory controller 0 162 * num| hi| clk| wrlvl | cpo |wrdata|2T 163 * ranks| mhz|adjst| start | |delay | 164 */ 165 {4, 850, 4, 6, 0xff, 2, 0}, 166 {4, 950, 5, 7, 0xff, 2, 0}, 167 {4, 1050, 5, 8, 0xff, 2, 0}, 168 {4, 1250, 5, 10, 0xff, 2, 0}, 169 {4, 1350, 5, 11, 0xff, 2, 0}, 170 {4, 1666, 5, 12, 0xff, 2, 0}, 171 {2, 850, 4, 6, 0xff, 2, 0}, 172 {2, 1050, 4, 7, 0xff, 2, 0}, 173 {2, 1666, 4, 8, 0xff, 2, 0}, 174 {1, 850, 4, 5, 0xff, 2, 0}, 175 {1, 950, 4, 7, 0xff, 2, 0}, 176 {1, 1666, 4, 8, 0xff, 2, 0}, 177 {} 178 }; 179 180 /* 181 * The two slots have slightly different timing. See comments above. 182 */ 183 static const struct board_specific_parameters *rdimms[] = { 184 rdimm0, 185 rdimm0, 186 }; 187 188 void fsl_ddr_board_options(memctl_options_t *popts, 189 dimm_params_t *pdimm, 190 unsigned int ctrl_num) 191 { 192 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 193 ulong ddr_freq; 194 195 if (ctrl_num > 1) { 196 printf("Wrong parameter for controller number %d", ctrl_num); 197 return; 198 } 199 if (!pdimm->n_ranks) 200 return; 201 202 if (popts->registered_dimm_en) 203 pbsp = rdimms[ctrl_num]; 204 else 205 pbsp = udimms[ctrl_num]; 206 207 208 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr 209 * freqency and n_banks specified in board_specific_parameters table. 210 */ 211 ddr_freq = get_ddr_freq(0) / 1000000; 212 while (pbsp->datarate_mhz_high) { 213 if (pbsp->n_ranks == pdimm->n_ranks) { 214 if (ddr_freq <= pbsp->datarate_mhz_high) { 215 popts->cpo_override = pbsp->cpo; 216 popts->write_data_delay = 217 pbsp->write_data_delay; 218 popts->clk_adjust = pbsp->clk_adjust; 219 popts->wrlvl_start = pbsp->wrlvl_start; 220 popts->twoT_en = pbsp->force_2T; 221 goto found; 222 } 223 pbsp_highest = pbsp; 224 } 225 pbsp++; 226 } 227 228 if (pbsp_highest) { 229 printf("Error: board specific timing not found " 230 "for data rate %lu MT/s!\n" 231 "Trying to use the highest speed (%u) parameters\n", 232 ddr_freq, pbsp_highest->datarate_mhz_high); 233 popts->cpo_override = pbsp_highest->cpo; 234 popts->write_data_delay = pbsp_highest->write_data_delay; 235 popts->clk_adjust = pbsp_highest->clk_adjust; 236 popts->wrlvl_start = pbsp_highest->wrlvl_start; 237 popts->twoT_en = pbsp_highest->force_2T; 238 } else { 239 panic("DIMM is not supported by this board"); 240 } 241 found: 242 /* 243 * Factors to consider for half-strength driver enable: 244 * - number of DIMMs installed 245 */ 246 popts->half_strength_driver_enable = 0; 247 /* 248 * Write leveling override 249 */ 250 popts->wrlvl_override = 1; 251 popts->wrlvl_sample = 0xf; 252 253 /* 254 * Rtt and Rtt_WR override 255 */ 256 popts->rtt_override = 0; 257 258 /* Enable ZQ calibration */ 259 popts->zq_en = 1; 260 261 /* DHC_EN =1, ODT = 60 Ohm */ 262 popts->ddr_cdr1 = DDR_CDR1_DHC_EN; 263 } 264 265 phys_size_t initdram(int board_type) 266 { 267 phys_size_t dram_size; 268 269 puts("Initializing...."); 270 271 if (fsl_use_spd()) { 272 puts("using SPD\n"); 273 dram_size = fsl_ddr_sdram(); 274 } else { 275 puts("using fixed parameters\n"); 276 dram_size = fixed_sdram(); 277 } 278 279 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 280 dram_size *= 0x100000; 281 282 debug(" DDR: "); 283 return dram_size; 284 } 285