1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <netdev.h> 26 #include <linux/compiler.h> 27 #include <asm/mmu.h> 28 #include <asm/processor.h> 29 #include <asm/cache.h> 30 #include <asm/immap_85xx.h> 31 #include <asm/fsl_law.h> 32 #include <asm/fsl_serdes.h> 33 #include <asm/fsl_portals.h> 34 #include <asm/fsl_liodn.h> 35 #include <fm_eth.h> 36 37 #include "../common/ngpixis.h" 38 #include "corenet_ds.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 int checkboard (void) 43 { 44 u8 sw; 45 struct cpu_type *cpu = gd->cpu; 46 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 47 unsigned int i; 48 static const char * const freq[] = {"100", "125", "156.25", "212.5" }; 49 50 printf("Board: %sDS, ", cpu->name); 51 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 52 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); 53 54 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); 55 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; 56 57 if (sw < 0x8) 58 printf("vBank: %d\n", sw); 59 else if (sw == 0x8) 60 puts("Promjet\n"); 61 else if (sw == 0x9) 62 puts("NAND\n"); 63 else 64 printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); 65 66 /* Display the RCW, so that no one gets confused as to what RCW 67 * we're actually using for this boot. 68 */ 69 puts("Reset Configuration Word (RCW):"); 70 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 71 u32 rcw = in_be32(&gur->rcwsr[i]); 72 73 if ((i % 4) == 0) 74 printf("\n %08x:", i * 4); 75 printf(" %08x", rcw); 76 } 77 puts("\n"); 78 79 /* Display the actual SERDES reference clocks as configured by the 80 * dip switches on the board. Note that the SWx registers could 81 * technically be set to force the reference clocks to match the 82 * values that the SERDES expects (or vice versa). For now, however, 83 * we just display both values and hope the user notices when they 84 * don't match. 85 */ 86 puts("SERDES Reference Clocks: "); 87 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ 88 || defined(CONFIG_P5040DS) 89 sw = in_8(&PIXIS_SW(5)); 90 for (i = 0; i < 3; i++) { 91 unsigned int clock = (sw >> (6 - (2 * i))) & 3; 92 93 printf("Bank%u=%sMhz ", i+1, freq[clock]); 94 } 95 #ifdef CONFIG_P5040DS 96 /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ 97 sw = in_8(&PIXIS_SW(9)); 98 printf("Bank4=%sMhz ", freq[sw & 3]); 99 #endif 100 puts("\n"); 101 #else 102 sw = in_8(&PIXIS_SW(3)); 103 /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ 104 /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ 105 /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ 106 printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]); 107 printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]); 108 printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]); 109 #endif 110 111 return 0; 112 } 113 114 int board_early_init_f(void) 115 { 116 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 117 118 /* 119 * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3 120 * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce 121 * the noise introduced by these unterminated and unused clock pairs. 122 */ 123 setbits_be32(&gur->ddrclkdr, 0x001B001B); 124 125 return 0; 126 } 127 128 int board_early_init_r(void) 129 { 130 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 131 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 132 133 /* 134 * Remap Boot flash + PROMJET region to caching-inhibited 135 * so that flash can be erased properly. 136 */ 137 138 /* Flush d-cache and invalidate i-cache of any FLASH data */ 139 flush_dcache(); 140 invalidate_icache(); 141 142 /* invalidate existing TLB entry for flash + promjet */ 143 disable_tlb(flash_esel); 144 145 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 146 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 147 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 148 149 set_liodns(); 150 #ifdef CONFIG_SYS_DPAA_QBMAN 151 setup_portals(); 152 #endif 153 154 return 0; 155 } 156 157 static const char *serdes_clock_to_string(u32 clock) 158 { 159 switch(clock) { 160 case SRDS_PLLCR0_RFCK_SEL_100: 161 return "100"; 162 case SRDS_PLLCR0_RFCK_SEL_125: 163 return "125"; 164 case SRDS_PLLCR0_RFCK_SEL_156_25: 165 return "156.25"; 166 default: 167 return "150"; 168 } 169 } 170 171 #define NUM_SRDS_BANKS 3 172 173 int misc_init_r(void) 174 { 175 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 176 u32 actual[NUM_SRDS_BANKS]; 177 unsigned int i; 178 u8 sw; 179 180 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ 181 || defined(CONFIG_P5040DS) 182 sw = in_8(&PIXIS_SW(5)); 183 for (i = 0; i < 3; i++) { 184 unsigned int clock = (sw >> (6 - (2 * i))) & 3; 185 switch (clock) { 186 case 0: 187 actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 188 break; 189 case 1: 190 actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 191 break; 192 case 2: 193 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; 194 break; 195 default: 196 printf("Warning: SDREFCLK%u switch setting of '11' is " 197 "unsupported\n", i + 1); 198 break; 199 } 200 } 201 #else 202 /* Warn if the expected SERDES reference clocks don't match the 203 * actual reference clocks. This needs to be done after calling 204 * p4080_erratum_serdes8(), since that function may modify the clocks. 205 */ 206 sw = in_8(&PIXIS_SW(3)); 207 actual[0] = (sw & 0x40) ? 208 SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; 209 actual[1] = (sw & 0x20) ? 210 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 211 actual[2] = (sw & 0x10) ? 212 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 213 #endif 214 215 for (i = 0; i < NUM_SRDS_BANKS; i++) { 216 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 217 if (expected != actual[i]) { 218 printf("Warning: SERDES bank %u expects reference clock" 219 " %sMHz, but actual is %sMHz\n", i + 1, 220 serdes_clock_to_string(expected), 221 serdes_clock_to_string(actual[i])); 222 } 223 } 224 225 return 0; 226 } 227 228 void ft_board_setup(void *blob, bd_t *bd) 229 { 230 phys_addr_t base; 231 phys_size_t size; 232 233 ft_cpu_setup(blob, bd); 234 235 base = getenv_bootm_low(); 236 size = getenv_bootm_size(); 237 238 fdt_fixup_memory(blob, (u64)base, (u64)size); 239 240 #ifdef CONFIG_PCI 241 pci_of_setup(blob, bd); 242 #endif 243 244 fdt_fixup_liodn(blob); 245 fdt_fixup_dr_usb(blob, bd); 246 247 #ifdef CONFIG_SYS_DPAA_FMAN 248 fdt_fixup_fman_ethernet(blob); 249 fdt_fixup_board_enet(blob); 250 #endif 251 } 252