1 /* 2 * Copyright 2009-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <netdev.h> 26 #include <linux/compiler.h> 27 #include <asm/mmu.h> 28 #include <asm/processor.h> 29 #include <asm/cache.h> 30 #include <asm/immap_85xx.h> 31 #include <asm/fsl_law.h> 32 #include <asm/fsl_serdes.h> 33 #include <asm/fsl_portals.h> 34 #include <asm/fsl_liodn.h> 35 36 extern void pci_of_setup(void *blob, bd_t *bd); 37 38 #include "../common/ngpixis.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 void cpu_mp_lmb_reserve(struct lmb *lmb); 43 44 int checkboard (void) 45 { 46 u8 sw; 47 struct cpu_type *cpu = gd->cpu; 48 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 49 unsigned int i; 50 51 printf("Board: %sDS, ", cpu->name); 52 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 53 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); 54 55 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); 56 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; 57 58 if (sw < 0x8) 59 printf("vBank: %d\n", sw); 60 else if (sw == 0x8) 61 puts("Promjet\n"); 62 else if (sw == 0x9) 63 puts("NAND\n"); 64 else 65 printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); 66 67 #ifdef CONFIG_PHYS_64BIT 68 puts("36-bit Addressing\n"); 69 #endif 70 71 /* Display the RCW, so that no one gets confused as to what RCW 72 * we're actually using for this boot. 73 */ 74 puts("Reset Configuration Word (RCW):"); 75 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 76 u32 rcw = in_be32(&gur->rcwsr[i]); 77 78 if ((i % 4) == 0) 79 printf("\n %08x:", i * 4); 80 printf(" %08x", rcw); 81 } 82 puts("\n"); 83 84 /* Display the actual SERDES reference clocks as configured by the 85 * dip switches on the board. Note that the SWx registers could 86 * technically be set to force the reference clocks to match the 87 * values that the SERDES expects (or vice versa). For now, however, 88 * we just display both values and hope the user notices when they 89 * don't match. 90 */ 91 puts("SERDES Reference Clocks: "); 92 sw = in_8(&PIXIS_SW(3)); 93 printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100); 94 printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125"); 95 printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125"); 96 97 return 0; 98 } 99 100 int board_early_init_f(void) 101 { 102 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 103 104 /* 105 * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3 106 * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce 107 * the noise introduced by these unterminated and unused clock pairs. 108 */ 109 setbits_be32(&gur->ddrclkdr, 0x001B001B); 110 111 return 0; 112 } 113 114 int board_early_init_r(void) 115 { 116 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 117 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 118 119 /* 120 * Remap Boot flash + PROMJET region to caching-inhibited 121 * so that flash can be erased properly. 122 */ 123 124 /* Flush d-cache and invalidate i-cache of any FLASH data */ 125 flush_dcache(); 126 invalidate_icache(); 127 128 /* invalidate existing TLB entry for flash + promjet */ 129 disable_tlb(flash_esel); 130 131 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 132 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 133 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 134 135 set_liodns(); 136 setup_portals(); 137 138 return 0; 139 } 140 141 static const char *serdes_clock_to_string(u32 clock) 142 { 143 switch(clock) { 144 case SRDS_PLLCR0_RFCK_SEL_100: 145 return "100"; 146 case SRDS_PLLCR0_RFCK_SEL_125: 147 return "125"; 148 case SRDS_PLLCR0_RFCK_SEL_156_25: 149 return "156.25"; 150 default: 151 return "???"; 152 } 153 } 154 155 #define NUM_SRDS_BANKS 3 156 157 int misc_init_r(void) 158 { 159 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 160 __maybe_unused ccsr_gur_t *gur; 161 u32 actual[NUM_SRDS_BANKS]; 162 unsigned int i; 163 u8 sw3; 164 165 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 166 #ifdef CONFIG_SRIO1 167 if (is_serdes_configured(SRIO1)) { 168 set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, 169 LAW_TRGT_IF_RIO_1); 170 } else { 171 printf (" SRIO1: disabled\n"); 172 } 173 #else 174 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ 175 #endif 176 177 #ifdef CONFIG_SRIO2 178 if (is_serdes_configured(SRIO2)) { 179 set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, 180 LAW_TRGT_IF_RIO_2); 181 } else { 182 printf (" SRIO2: disabled\n"); 183 } 184 #else 185 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ 186 #endif 187 188 /* Warn if the expected SERDES reference clocks don't match the 189 * actual reference clocks. This needs to be done after calling 190 * p4080_erratum_serdes8(), since that function may modify the clocks. 191 */ 192 sw3 = in_8(&PIXIS_SW(3)); 193 actual[0] = (sw3 & 0x40) ? 194 SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; 195 actual[1] = (sw3 & 0x20) ? 196 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 197 actual[2] = (sw3 & 0x10) ? 198 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 199 200 for (i = 0; i < NUM_SRDS_BANKS; i++) { 201 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 202 if (expected != actual[i]) { 203 printf("Warning: SERDES bank %u expects reference clock" 204 " %sMHz, but actual is %sMHz\n", i + 1, 205 serdes_clock_to_string(expected), 206 serdes_clock_to_string(actual[i])); 207 } 208 } 209 210 return 0; 211 } 212 213 #ifdef CONFIG_MP 214 void board_lmb_reserve(struct lmb *lmb) 215 { 216 cpu_mp_lmb_reserve(lmb); 217 } 218 #endif 219 220 void ft_srio_setup(void *blob) 221 { 222 #ifdef CONFIG_SRIO1 223 if (!is_serdes_configured(SRIO1)) { 224 fdt_del_node_and_alias(blob, "rio0"); 225 } 226 #else 227 fdt_del_node_and_alias(blob, "rio0"); 228 #endif 229 #ifdef CONFIG_SRIO2 230 if (!is_serdes_configured(SRIO2)) { 231 fdt_del_node_and_alias(blob, "rio1"); 232 } 233 #else 234 fdt_del_node_and_alias(blob, "rio1"); 235 #endif 236 } 237 238 void ft_board_setup(void *blob, bd_t *bd) 239 { 240 phys_addr_t base; 241 phys_size_t size; 242 243 ft_cpu_setup(blob, bd); 244 245 ft_srio_setup(blob); 246 247 base = getenv_bootm_low(); 248 size = getenv_bootm_size(); 249 250 fdt_fixup_memory(blob, (u64)base, (u64)size); 251 252 #ifdef CONFIG_PCI 253 pci_of_setup(blob, bd); 254 #endif 255 256 fdt_fixup_liodn(blob); 257 } 258 259 int board_eth_init(bd_t *bis) 260 { 261 return pci_eth_init(bis); 262 } 263