1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <netdev.h> 26 #include <linux/compiler.h> 27 #include <asm/mmu.h> 28 #include <asm/processor.h> 29 #include <asm/cache.h> 30 #include <asm/immap_85xx.h> 31 #include <asm/fsl_law.h> 32 #include <asm/fsl_serdes.h> 33 #include <asm/fsl_portals.h> 34 #include <asm/fsl_liodn.h> 35 #include <fm_eth.h> 36 37 #include "../common/ngpixis.h" 38 #include "corenet_ds.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 int checkboard (void) 43 { 44 u8 sw; 45 struct cpu_type *cpu = gd->cpu; 46 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 47 unsigned int i; 48 49 printf("Board: %sDS, ", cpu->name); 50 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 51 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); 52 53 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); 54 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; 55 56 if (sw < 0x8) 57 printf("vBank: %d\n", sw); 58 else if (sw == 0x8) 59 puts("Promjet\n"); 60 else if (sw == 0x9) 61 puts("NAND\n"); 62 else 63 printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); 64 65 /* Display the RCW, so that no one gets confused as to what RCW 66 * we're actually using for this boot. 67 */ 68 puts("Reset Configuration Word (RCW):"); 69 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 70 u32 rcw = in_be32(&gur->rcwsr[i]); 71 72 if ((i % 4) == 0) 73 printf("\n %08x:", i * 4); 74 printf(" %08x", rcw); 75 } 76 puts("\n"); 77 78 /* Display the actual SERDES reference clocks as configured by the 79 * dip switches on the board. Note that the SWx registers could 80 * technically be set to force the reference clocks to match the 81 * values that the SERDES expects (or vice versa). For now, however, 82 * we just display both values and hope the user notices when they 83 * don't match. 84 */ 85 puts("SERDES Reference Clocks: "); 86 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) 87 sw = in_8(&PIXIS_SW(5)); 88 for (i = 0; i < 3; i++) { 89 static const char *freq[] = {"100", "125", "156.25", "212.5" }; 90 unsigned int clock = (sw >> (6 - (2 * i))) & 3; 91 92 printf("Bank%u=%sMhz ", i+1, freq[clock]); 93 } 94 puts("\n"); 95 #else 96 sw = in_8(&PIXIS_SW(3)); 97 printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100); 98 printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125"); 99 printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125"); 100 #endif 101 102 return 0; 103 } 104 105 int board_early_init_f(void) 106 { 107 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 108 109 /* 110 * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3 111 * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce 112 * the noise introduced by these unterminated and unused clock pairs. 113 */ 114 setbits_be32(&gur->ddrclkdr, 0x001B001B); 115 116 return 0; 117 } 118 119 int board_early_init_r(void) 120 { 121 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 122 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 123 124 /* 125 * Remap Boot flash + PROMJET region to caching-inhibited 126 * so that flash can be erased properly. 127 */ 128 129 /* Flush d-cache and invalidate i-cache of any FLASH data */ 130 flush_dcache(); 131 invalidate_icache(); 132 133 /* invalidate existing TLB entry for flash + promjet */ 134 disable_tlb(flash_esel); 135 136 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 137 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 138 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 139 140 set_liodns(); 141 #ifdef CONFIG_SYS_DPAA_QBMAN 142 setup_portals(); 143 #endif 144 145 return 0; 146 } 147 148 static const char *serdes_clock_to_string(u32 clock) 149 { 150 switch(clock) { 151 case SRDS_PLLCR0_RFCK_SEL_100: 152 return "100"; 153 case SRDS_PLLCR0_RFCK_SEL_125: 154 return "125"; 155 case SRDS_PLLCR0_RFCK_SEL_156_25: 156 return "156.25"; 157 default: 158 return "150"; 159 } 160 } 161 162 #define NUM_SRDS_BANKS 3 163 164 int misc_init_r(void) 165 { 166 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 167 u32 actual[NUM_SRDS_BANKS]; 168 unsigned int i; 169 u8 sw; 170 171 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) 172 sw = in_8(&PIXIS_SW(5)); 173 for (i = 0; i < 3; i++) { 174 unsigned int clock = (sw >> (6 - (2 * i))) & 3; 175 switch (clock) { 176 case 0: 177 actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 178 break; 179 case 1: 180 actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 181 break; 182 case 2: 183 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; 184 break; 185 default: 186 printf("Warning: SDREFCLK%u switch setting of '11' is " 187 "unsupported\n", i + 1); 188 break; 189 } 190 } 191 #else 192 /* Warn if the expected SERDES reference clocks don't match the 193 * actual reference clocks. This needs to be done after calling 194 * p4080_erratum_serdes8(), since that function may modify the clocks. 195 */ 196 sw = in_8(&PIXIS_SW(3)); 197 actual[0] = (sw & 0x40) ? 198 SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; 199 actual[1] = (sw & 0x20) ? 200 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 201 actual[2] = (sw & 0x10) ? 202 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 203 #endif 204 205 for (i = 0; i < NUM_SRDS_BANKS; i++) { 206 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 207 if (expected != actual[i]) { 208 printf("Warning: SERDES bank %u expects reference clock" 209 " %sMHz, but actual is %sMHz\n", i + 1, 210 serdes_clock_to_string(expected), 211 serdes_clock_to_string(actual[i])); 212 } 213 } 214 215 return 0; 216 } 217 218 void ft_board_setup(void *blob, bd_t *bd) 219 { 220 phys_addr_t base; 221 phys_size_t size; 222 223 ft_cpu_setup(blob, bd); 224 225 base = getenv_bootm_low(); 226 size = getenv_bootm_size(); 227 228 fdt_fixup_memory(blob, (u64)base, (u64)size); 229 230 #ifdef CONFIG_PCI 231 pci_of_setup(blob, bd); 232 #endif 233 234 fdt_fixup_liodn(blob); 235 fdt_fixup_dr_usb(blob, bd); 236 237 #ifdef CONFIG_SYS_DPAA_FMAN 238 fdt_fixup_fman_ethernet(blob); 239 fdt_fixup_board_enet(blob); 240 #endif 241 } 242