1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <netdev.h> 26 #include <linux/compiler.h> 27 #include <asm/mmu.h> 28 #include <asm/processor.h> 29 #include <asm/cache.h> 30 #include <asm/immap_85xx.h> 31 #include <asm/fsl_law.h> 32 #include <asm/fsl_serdes.h> 33 #include <asm/fsl_portals.h> 34 #include <asm/fsl_liodn.h> 35 #include <fm_eth.h> 36 37 #include "../common/ngpixis.h" 38 #include "corenet_ds.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 int checkboard (void) 43 { 44 u8 sw; 45 struct cpu_type *cpu = gd->cpu; 46 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 47 unsigned int i; 48 49 printf("Board: %sDS, ", cpu->name); 50 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 51 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); 52 53 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); 54 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; 55 56 if (sw < 0x8) 57 printf("vBank: %d\n", sw); 58 else if (sw == 0x8) 59 puts("Promjet\n"); 60 else if (sw == 0x9) 61 puts("NAND\n"); 62 else 63 printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); 64 65 #ifdef CONFIG_PHYS_64BIT 66 puts("36-bit Addressing\n"); 67 #endif 68 69 /* Display the RCW, so that no one gets confused as to what RCW 70 * we're actually using for this boot. 71 */ 72 puts("Reset Configuration Word (RCW):"); 73 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 74 u32 rcw = in_be32(&gur->rcwsr[i]); 75 76 if ((i % 4) == 0) 77 printf("\n %08x:", i * 4); 78 printf(" %08x", rcw); 79 } 80 puts("\n"); 81 82 /* Display the actual SERDES reference clocks as configured by the 83 * dip switches on the board. Note that the SWx registers could 84 * technically be set to force the reference clocks to match the 85 * values that the SERDES expects (or vice versa). For now, however, 86 * we just display both values and hope the user notices when they 87 * don't match. 88 */ 89 puts("SERDES Reference Clocks: "); 90 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) 91 sw = in_8(&PIXIS_SW(5)); 92 for (i = 0; i < 3; i++) { 93 static const char *freq[] = {"100", "125", "156.25", "212.5" }; 94 unsigned int clock = (sw >> (6 - (2 * i))) & 3; 95 96 printf("Bank%u=%sMhz ", i+1, freq[clock]); 97 } 98 puts("\n"); 99 #else 100 sw = in_8(&PIXIS_SW(3)); 101 printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100); 102 printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125"); 103 printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125"); 104 #endif 105 106 return 0; 107 } 108 109 int board_early_init_f(void) 110 { 111 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 112 113 /* 114 * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3 115 * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce 116 * the noise introduced by these unterminated and unused clock pairs. 117 */ 118 setbits_be32(&gur->ddrclkdr, 0x001B001B); 119 120 return 0; 121 } 122 123 int board_early_init_r(void) 124 { 125 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 126 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 127 128 /* 129 * Remap Boot flash + PROMJET region to caching-inhibited 130 * so that flash can be erased properly. 131 */ 132 133 /* Flush d-cache and invalidate i-cache of any FLASH data */ 134 flush_dcache(); 135 invalidate_icache(); 136 137 /* invalidate existing TLB entry for flash + promjet */ 138 disable_tlb(flash_esel); 139 140 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 141 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 142 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 143 144 set_liodns(); 145 #ifdef CONFIG_SYS_DPAA_QBMAN 146 setup_portals(); 147 #endif 148 149 return 0; 150 } 151 152 static const char *serdes_clock_to_string(u32 clock) 153 { 154 switch(clock) { 155 case SRDS_PLLCR0_RFCK_SEL_100: 156 return "100"; 157 case SRDS_PLLCR0_RFCK_SEL_125: 158 return "125"; 159 case SRDS_PLLCR0_RFCK_SEL_156_25: 160 return "156.25"; 161 default: 162 return "150"; 163 } 164 } 165 166 #define NUM_SRDS_BANKS 3 167 168 int misc_init_r(void) 169 { 170 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 171 u32 actual[NUM_SRDS_BANKS]; 172 unsigned int i; 173 u8 sw; 174 175 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) 176 sw = in_8(&PIXIS_SW(5)); 177 for (i = 0; i < 3; i++) { 178 unsigned int clock = (sw >> (6 - (2 * i))) & 3; 179 switch (clock) { 180 case 0: 181 actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 182 break; 183 case 1: 184 actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 185 break; 186 case 2: 187 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; 188 break; 189 default: 190 printf("Warning: SDREFCLK%u switch setting of '11' is " 191 "unsupported\n", i + 1); 192 break; 193 } 194 } 195 #else 196 /* Warn if the expected SERDES reference clocks don't match the 197 * actual reference clocks. This needs to be done after calling 198 * p4080_erratum_serdes8(), since that function may modify the clocks. 199 */ 200 sw = in_8(&PIXIS_SW(3)); 201 actual[0] = (sw & 0x40) ? 202 SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; 203 actual[1] = (sw & 0x20) ? 204 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 205 actual[2] = (sw & 0x10) ? 206 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 207 #endif 208 209 for (i = 0; i < NUM_SRDS_BANKS; i++) { 210 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 211 if (expected != actual[i]) { 212 printf("Warning: SERDES bank %u expects reference clock" 213 " %sMHz, but actual is %sMHz\n", i + 1, 214 serdes_clock_to_string(expected), 215 serdes_clock_to_string(actual[i])); 216 } 217 } 218 219 return 0; 220 } 221 222 void ft_board_setup(void *blob, bd_t *bd) 223 { 224 phys_addr_t base; 225 phys_size_t size; 226 227 ft_cpu_setup(blob, bd); 228 229 base = getenv_bootm_low(); 230 size = getenv_bootm_size(); 231 232 fdt_fixup_memory(blob, (u64)base, (u64)size); 233 234 #ifdef CONFIG_PCI 235 pci_of_setup(blob, bd); 236 #endif 237 238 fdt_fixup_liodn(blob); 239 fdt_fixup_dr_usb(blob, bd); 240 241 #ifdef CONFIG_SYS_DPAA_FMAN 242 fdt_fixup_fman_ethernet(blob); 243 fdt_fixup_board_enet(blob); 244 #endif 245 } 246