1 /* 2 * Copyright 2009-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <netdev.h> 26 #include <linux/compiler.h> 27 #include <asm/mmu.h> 28 #include <asm/processor.h> 29 #include <asm/cache.h> 30 #include <asm/immap_85xx.h> 31 #include <asm/fsl_law.h> 32 #include <asm/fsl_serdes.h> 33 #include <asm/fsl_portals.h> 34 #include <asm/fsl_liodn.h> 35 36 extern void pci_of_setup(void *blob, bd_t *bd); 37 38 #include "../common/ngpixis.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 void cpu_mp_lmb_reserve(struct lmb *lmb); 43 44 int checkboard (void) 45 { 46 u8 sw; 47 struct cpu_type *cpu = gd->cpu; 48 49 printf("Board: %sDS, ", cpu->name); 50 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 51 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); 52 53 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); 54 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; 55 56 if (sw < 0x8) 57 printf("vBank: %d\n", sw); 58 else if (sw == 0x8) 59 puts("Promjet\n"); 60 else if (sw == 0x9) 61 puts("NAND\n"); 62 else 63 printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); 64 65 #ifdef CONFIG_PHYS_64BIT 66 puts("36-bit Addressing\n"); 67 #endif 68 69 /* Display the actual SERDES reference clocks as configured by the 70 * dip switches on the board. Note that the SWx registers could 71 * technically be set to force the reference clocks to match the 72 * values that the SERDES expects (or vice versa). For now, however, 73 * we just display both values and hope the user notices when they 74 * don't match. 75 */ 76 puts("SERDES Reference Clocks: "); 77 sw = in_8(&PIXIS_SW(3)); 78 printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100); 79 printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125"); 80 printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125"); 81 82 return 0; 83 } 84 85 int board_early_init_f(void) 86 { 87 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 88 89 /* 90 * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3 91 * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce 92 * the noise introduced by these unterminated and unused clock pairs. 93 */ 94 setbits_be32(&gur->ddrclkdr, 0x001B001B); 95 96 return 0; 97 } 98 99 int board_early_init_r(void) 100 { 101 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 102 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 103 104 /* 105 * Remap Boot flash + PROMJET region to caching-inhibited 106 * so that flash can be erased properly. 107 */ 108 109 /* Flush d-cache and invalidate i-cache of any FLASH data */ 110 flush_dcache(); 111 invalidate_icache(); 112 113 /* invalidate existing TLB entry for flash + promjet */ 114 disable_tlb(flash_esel); 115 116 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 117 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 118 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 119 120 set_liodns(); 121 setup_portals(); 122 123 return 0; 124 } 125 126 static const char *serdes_clock_to_string(u32 clock) 127 { 128 switch(clock) { 129 case SRDS_PLLCR0_RFCK_SEL_100: 130 return "100"; 131 case SRDS_PLLCR0_RFCK_SEL_125: 132 return "125"; 133 case SRDS_PLLCR0_RFCK_SEL_156_25: 134 return "156.25"; 135 default: 136 return "???"; 137 } 138 } 139 140 #define NUM_SRDS_BANKS 3 141 142 int misc_init_r(void) 143 { 144 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 145 __maybe_unused ccsr_gur_t *gur; 146 u32 actual[NUM_SRDS_BANKS]; 147 unsigned int i; 148 u8 sw3; 149 150 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 151 #ifdef CONFIG_SRIO1 152 if (is_serdes_configured(SRIO1)) { 153 set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, 154 LAW_TRGT_IF_RIO_1); 155 } else { 156 printf (" SRIO1: disabled\n"); 157 } 158 #else 159 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ 160 #endif 161 162 #ifdef CONFIG_SRIO2 163 if (is_serdes_configured(SRIO2)) { 164 set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, 165 LAW_TRGT_IF_RIO_2); 166 } else { 167 printf (" SRIO2: disabled\n"); 168 } 169 #else 170 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ 171 #endif 172 173 /* Warn if the expected SERDES reference clocks don't match the 174 * actual reference clocks. This needs to be done after calling 175 * p4080_erratum_serdes8(), since that function may modify the clocks. 176 */ 177 sw3 = in_8(&PIXIS_SW(3)); 178 actual[0] = (sw3 & 0x40) ? 179 SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; 180 actual[1] = (sw3 & 0x20) ? 181 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 182 actual[2] = (sw3 & 0x10) ? 183 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 184 185 for (i = 0; i < NUM_SRDS_BANKS; i++) { 186 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 187 if (expected != actual[i]) { 188 printf("Warning: SERDES bank %u expects reference clock" 189 " %sMHz, but actual is %sMHz\n", i + 1, 190 serdes_clock_to_string(expected), 191 serdes_clock_to_string(actual[i])); 192 } 193 } 194 195 return 0; 196 } 197 198 #ifdef CONFIG_MP 199 void board_lmb_reserve(struct lmb *lmb) 200 { 201 cpu_mp_lmb_reserve(lmb); 202 } 203 #endif 204 205 void ft_srio_setup(void *blob) 206 { 207 #ifdef CONFIG_SRIO1 208 if (!is_serdes_configured(SRIO1)) { 209 fdt_del_node_and_alias(blob, "rio0"); 210 } 211 #else 212 fdt_del_node_and_alias(blob, "rio0"); 213 #endif 214 #ifdef CONFIG_SRIO2 215 if (!is_serdes_configured(SRIO2)) { 216 fdt_del_node_and_alias(blob, "rio1"); 217 } 218 #else 219 fdt_del_node_and_alias(blob, "rio1"); 220 #endif 221 } 222 223 void ft_board_setup(void *blob, bd_t *bd) 224 { 225 phys_addr_t base; 226 phys_size_t size; 227 228 ft_cpu_setup(blob, bd); 229 230 ft_srio_setup(blob); 231 232 base = getenv_bootm_low(); 233 size = getenv_bootm_size(); 234 235 fdt_fixup_memory(blob, (u64)base, (u64)size); 236 237 #ifdef CONFIG_PCI 238 pci_of_setup(blob, bd); 239 #endif 240 241 fdt_fixup_liodn(blob); 242 } 243 244 int board_eth_init(bd_t *bis) 245 { 246 return pci_eth_init(bis); 247 } 248