1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <netdev.h> 10 #include <linux/compiler.h> 11 #include <asm/mmu.h> 12 #include <asm/processor.h> 13 #include <asm/cache.h> 14 #include <asm/immap_85xx.h> 15 #include <asm/fsl_law.h> 16 #include <asm/fsl_serdes.h> 17 #include <asm/fsl_portals.h> 18 #include <asm/fsl_liodn.h> 19 #include <fm_eth.h> 20 21 #include "../common/ngpixis.h" 22 #include "corenet_ds.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 int checkboard (void) 27 { 28 u8 sw; 29 struct cpu_type *cpu = gd->arch.cpu; 30 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 31 unsigned int i; 32 static const char * const freq[] = {"100", "125", "156.25", "212.5" }; 33 34 printf("Board: %sDS, ", cpu->name); 35 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 36 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); 37 38 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); 39 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; 40 41 if (sw < 0x8) 42 printf("vBank: %d\n", sw); 43 else if (sw == 0x8) 44 puts("Promjet\n"); 45 else if (sw == 0x9) 46 puts("NAND\n"); 47 else 48 printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); 49 50 /* Display the RCW, so that no one gets confused as to what RCW 51 * we're actually using for this boot. 52 */ 53 puts("Reset Configuration Word (RCW):"); 54 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 55 u32 rcw = in_be32(&gur->rcwsr[i]); 56 57 if ((i % 4) == 0) 58 printf("\n %08x:", i * 4); 59 printf(" %08x", rcw); 60 } 61 puts("\n"); 62 63 /* Display the actual SERDES reference clocks as configured by the 64 * dip switches on the board. Note that the SWx registers could 65 * technically be set to force the reference clocks to match the 66 * values that the SERDES expects (or vice versa). For now, however, 67 * we just display both values and hope the user notices when they 68 * don't match. 69 */ 70 puts("SERDES Reference Clocks: "); 71 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ 72 || defined(CONFIG_P5040DS) 73 sw = in_8(&PIXIS_SW(5)); 74 for (i = 0; i < 3; i++) { 75 unsigned int clock = (sw >> (6 - (2 * i))) & 3; 76 77 printf("Bank%u=%sMhz ", i+1, freq[clock]); 78 } 79 #ifdef CONFIG_P5040DS 80 /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ 81 sw = in_8(&PIXIS_SW(9)); 82 printf("Bank4=%sMhz ", freq[sw & 3]); 83 #endif 84 puts("\n"); 85 #else 86 sw = in_8(&PIXIS_SW(3)); 87 /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ 88 /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ 89 /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ 90 printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]); 91 printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]); 92 printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]); 93 #endif 94 95 return 0; 96 } 97 98 int board_early_init_f(void) 99 { 100 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 101 102 /* 103 * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3 104 * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce 105 * the noise introduced by these unterminated and unused clock pairs. 106 */ 107 setbits_be32(&gur->ddrclkdr, 0x001B001B); 108 109 return 0; 110 } 111 112 int board_early_init_r(void) 113 { 114 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 115 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 116 117 /* 118 * Remap Boot flash + PROMJET region to caching-inhibited 119 * so that flash can be erased properly. 120 */ 121 122 /* Flush d-cache and invalidate i-cache of any FLASH data */ 123 flush_dcache(); 124 invalidate_icache(); 125 126 /* invalidate existing TLB entry for flash + promjet */ 127 disable_tlb(flash_esel); 128 129 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 130 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 131 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 132 133 set_liodns(); 134 #ifdef CONFIG_SYS_DPAA_QBMAN 135 setup_portals(); 136 #endif 137 138 return 0; 139 } 140 141 static const char *serdes_clock_to_string(u32 clock) 142 { 143 switch(clock) { 144 case SRDS_PLLCR0_RFCK_SEL_100: 145 return "100"; 146 case SRDS_PLLCR0_RFCK_SEL_125: 147 return "125"; 148 case SRDS_PLLCR0_RFCK_SEL_156_25: 149 return "156.25"; 150 default: 151 return "150"; 152 } 153 } 154 155 #define NUM_SRDS_BANKS 3 156 157 int misc_init_r(void) 158 { 159 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 160 u32 actual[NUM_SRDS_BANKS]; 161 unsigned int i; 162 u8 sw; 163 164 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ 165 || defined(CONFIG_P5040DS) 166 sw = in_8(&PIXIS_SW(5)); 167 for (i = 0; i < 3; i++) { 168 unsigned int clock = (sw >> (6 - (2 * i))) & 3; 169 switch (clock) { 170 case 0: 171 actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 172 break; 173 case 1: 174 actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 175 break; 176 case 2: 177 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; 178 break; 179 default: 180 printf("Warning: SDREFCLK%u switch setting of '11' is " 181 "unsupported\n", i + 1); 182 break; 183 } 184 } 185 #else 186 /* Warn if the expected SERDES reference clocks don't match the 187 * actual reference clocks. This needs to be done after calling 188 * p4080_erratum_serdes8(), since that function may modify the clocks. 189 */ 190 sw = in_8(&PIXIS_SW(3)); 191 actual[0] = (sw & 0x40) ? 192 SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; 193 actual[1] = (sw & 0x20) ? 194 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 195 actual[2] = (sw & 0x10) ? 196 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 197 #endif 198 199 for (i = 0; i < NUM_SRDS_BANKS; i++) { 200 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 201 if (expected != actual[i]) { 202 printf("Warning: SERDES bank %u expects reference clock" 203 " %sMHz, but actual is %sMHz\n", i + 1, 204 serdes_clock_to_string(expected), 205 serdes_clock_to_string(actual[i])); 206 } 207 } 208 209 return 0; 210 } 211 212 void ft_board_setup(void *blob, bd_t *bd) 213 { 214 phys_addr_t base; 215 phys_size_t size; 216 217 ft_cpu_setup(blob, bd); 218 219 base = getenv_bootm_low(); 220 size = getenv_bootm_size(); 221 222 fdt_fixup_memory(blob, (u64)base, (u64)size); 223 224 #ifdef CONFIG_PCI 225 pci_of_setup(blob, bd); 226 #endif 227 228 fdt_fixup_liodn(blob); 229 fdt_fixup_dr_usb(blob, bd); 230 231 #ifdef CONFIG_SYS_DPAA_FMAN 232 fdt_fixup_fman_ethernet(blob); 233 fdt_fixup_board_enet(blob); 234 #endif 235 } 236