1d1712369SKumar Gala /* 2561e710aSKumar Gala * Copyright 2009-2011 Freescale Semiconductor, Inc. 3d1712369SKumar Gala * 4d1712369SKumar Gala * See file CREDITS for list of people who contributed to this 5d1712369SKumar Gala * project. 6d1712369SKumar Gala * 7d1712369SKumar Gala * This program is free software; you can redistribute it and/or 8d1712369SKumar Gala * modify it under the terms of the GNU General Public License as 9d1712369SKumar Gala * published by the Free Software Foundation; either version 2 of 10d1712369SKumar Gala * the License, or (at your option) any later version. 11d1712369SKumar Gala * 12d1712369SKumar Gala * This program is distributed in the hope that it will be useful, 13d1712369SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 14d1712369SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15d1712369SKumar Gala * GNU General Public License for more details. 16d1712369SKumar Gala * 17d1712369SKumar Gala * You should have received a copy of the GNU General Public License 18d1712369SKumar Gala * along with this program; if not, write to the Free Software 19d1712369SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20d1712369SKumar Gala * MA 02111-1307 USA 21d1712369SKumar Gala */ 22d1712369SKumar Gala 23d1712369SKumar Gala #include <common.h> 24d1712369SKumar Gala #include <command.h> 25d1712369SKumar Gala #include <netdev.h> 260e159024SLian Minghuan #include <linux/compiler.h> 27d1712369SKumar Gala #include <asm/mmu.h> 28d1712369SKumar Gala #include <asm/processor.h> 29d1712369SKumar Gala #include <asm/cache.h> 30d1712369SKumar Gala #include <asm/immap_85xx.h> 31d1712369SKumar Gala #include <asm/fsl_law.h> 32d1712369SKumar Gala #include <asm/fsl_serdes.h> 33d1712369SKumar Gala #include <asm/fsl_portals.h> 34d1712369SKumar Gala #include <asm/fsl_liodn.h> 352915609aSAndy Fleming #include <fm_eth.h> 36d1712369SKumar Gala 37d1712369SKumar Gala #include "../common/ngpixis.h" 382915609aSAndy Fleming #include "corenet_ds.h" 39d1712369SKumar Gala 40d1712369SKumar Gala DECLARE_GLOBAL_DATA_PTR; 41d1712369SKumar Gala 42d1712369SKumar Gala int checkboard (void) 43d1712369SKumar Gala { 44d1712369SKumar Gala u8 sw; 45d1712369SKumar Gala struct cpu_type *cpu = gd->cpu; 4646299078STimur Tabi ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 4746299078STimur Tabi unsigned int i; 48*d31e53b4STimur Tabi static const char * const freq[] = {"100", "125", "156.25", "212.5" }; 49d1712369SKumar Gala 50d1712369SKumar Gala printf("Board: %sDS, ", cpu->name); 51d1712369SKumar Gala printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 52d1712369SKumar Gala in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); 53d1712369SKumar Gala 54d1712369SKumar Gala sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); 55d1712369SKumar Gala sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; 56d1712369SKumar Gala 57d1712369SKumar Gala if (sw < 0x8) 58d1712369SKumar Gala printf("vBank: %d\n", sw); 59d1712369SKumar Gala else if (sw == 0x8) 60d1712369SKumar Gala puts("Promjet\n"); 61d1712369SKumar Gala else if (sw == 0x9) 62d1712369SKumar Gala puts("NAND\n"); 63d1712369SKumar Gala else 64d1712369SKumar Gala printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); 65d1712369SKumar Gala 6646299078STimur Tabi /* Display the RCW, so that no one gets confused as to what RCW 6746299078STimur Tabi * we're actually using for this boot. 6846299078STimur Tabi */ 6946299078STimur Tabi puts("Reset Configuration Word (RCW):"); 7046299078STimur Tabi for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 7146299078STimur Tabi u32 rcw = in_be32(&gur->rcwsr[i]); 7246299078STimur Tabi 7346299078STimur Tabi if ((i % 4) == 0) 7446299078STimur Tabi printf("\n %08x:", i * 4); 7546299078STimur Tabi printf(" %08x", rcw); 7646299078STimur Tabi } 7746299078STimur Tabi puts("\n"); 7846299078STimur Tabi 79d1712369SKumar Gala /* Display the actual SERDES reference clocks as configured by the 80d1712369SKumar Gala * dip switches on the board. Note that the SWx registers could 81d1712369SKumar Gala * technically be set to force the reference clocks to match the 82d1712369SKumar Gala * values that the SERDES expects (or vice versa). For now, however, 83d1712369SKumar Gala * we just display both values and hope the user notices when they 84d1712369SKumar Gala * don't match. 85d1712369SKumar Gala */ 86d1712369SKumar Gala puts("SERDES Reference Clocks: "); 87*d31e53b4STimur Tabi #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ 88*d31e53b4STimur Tabi || defined(CONFIG_P5040DS) 89e02aea61SKumar Gala sw = in_8(&PIXIS_SW(5)); 90e02aea61SKumar Gala for (i = 0; i < 3; i++) { 91e02aea61SKumar Gala unsigned int clock = (sw >> (6 - (2 * i))) & 3; 92e02aea61SKumar Gala 93e02aea61SKumar Gala printf("Bank%u=%sMhz ", i+1, freq[clock]); 94e02aea61SKumar Gala } 95*d31e53b4STimur Tabi #ifdef CONFIG_P5040DS 96*d31e53b4STimur Tabi /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ 97*d31e53b4STimur Tabi sw = in_8(&PIXIS_SW(9)); 98*d31e53b4STimur Tabi printf("Bank4=%sMhz ", freq[sw & 3]); 99*d31e53b4STimur Tabi #endif 100e02aea61SKumar Gala puts("\n"); 101e02aea61SKumar Gala #else 102d1712369SKumar Gala sw = in_8(&PIXIS_SW(3)); 103*d31e53b4STimur Tabi /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ 104*d31e53b4STimur Tabi /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ 105*d31e53b4STimur Tabi /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ 106*d31e53b4STimur Tabi printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]); 107*d31e53b4STimur Tabi printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]); 108*d31e53b4STimur Tabi printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]); 109e02aea61SKumar Gala #endif 110d1712369SKumar Gala 111d1712369SKumar Gala return 0; 112d1712369SKumar Gala } 113d1712369SKumar Gala 114d1712369SKumar Gala int board_early_init_f(void) 115d1712369SKumar Gala { 116d1712369SKumar Gala volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 117d1712369SKumar Gala 118d1712369SKumar Gala /* 119d1712369SKumar Gala * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3 120d1712369SKumar Gala * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce 121d1712369SKumar Gala * the noise introduced by these unterminated and unused clock pairs. 122d1712369SKumar Gala */ 123d1712369SKumar Gala setbits_be32(&gur->ddrclkdr, 0x001B001B); 124d1712369SKumar Gala 125d1712369SKumar Gala return 0; 126d1712369SKumar Gala } 127d1712369SKumar Gala 128d1712369SKumar Gala int board_early_init_r(void) 129d1712369SKumar Gala { 130d1712369SKumar Gala const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 131d1712369SKumar Gala const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 132d1712369SKumar Gala 133d1712369SKumar Gala /* 134d1712369SKumar Gala * Remap Boot flash + PROMJET region to caching-inhibited 135d1712369SKumar Gala * so that flash can be erased properly. 136d1712369SKumar Gala */ 137d1712369SKumar Gala 138d1712369SKumar Gala /* Flush d-cache and invalidate i-cache of any FLASH data */ 139d1712369SKumar Gala flush_dcache(); 140d1712369SKumar Gala invalidate_icache(); 141d1712369SKumar Gala 142d1712369SKumar Gala /* invalidate existing TLB entry for flash + promjet */ 143d1712369SKumar Gala disable_tlb(flash_esel); 144d1712369SKumar Gala 145d1712369SKumar Gala set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 146d1712369SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 147d1712369SKumar Gala 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 148d1712369SKumar Gala 149d1712369SKumar Gala set_liodns(); 15058b2f96eSKumar Gala #ifdef CONFIG_SYS_DPAA_QBMAN 151d1712369SKumar Gala setup_portals(); 15258b2f96eSKumar Gala #endif 153d1712369SKumar Gala 154d1712369SKumar Gala return 0; 155d1712369SKumar Gala } 156d1712369SKumar Gala 157d1712369SKumar Gala static const char *serdes_clock_to_string(u32 clock) 158d1712369SKumar Gala { 159d1712369SKumar Gala switch(clock) { 160d1712369SKumar Gala case SRDS_PLLCR0_RFCK_SEL_100: 161d1712369SKumar Gala return "100"; 162d1712369SKumar Gala case SRDS_PLLCR0_RFCK_SEL_125: 163d1712369SKumar Gala return "125"; 164d1712369SKumar Gala case SRDS_PLLCR0_RFCK_SEL_156_25: 165d1712369SKumar Gala return "156.25"; 166d1712369SKumar Gala default: 167e02aea61SKumar Gala return "150"; 168d1712369SKumar Gala } 169d1712369SKumar Gala } 170d1712369SKumar Gala 171d1712369SKumar Gala #define NUM_SRDS_BANKS 3 172d1712369SKumar Gala 173d1712369SKumar Gala int misc_init_r(void) 174d1712369SKumar Gala { 175d1712369SKumar Gala serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 176d1712369SKumar Gala u32 actual[NUM_SRDS_BANKS]; 177d1712369SKumar Gala unsigned int i; 178e02aea61SKumar Gala u8 sw; 179d1712369SKumar Gala 180*d31e53b4STimur Tabi #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ 181*d31e53b4STimur Tabi || defined(CONFIG_P5040DS) 182e02aea61SKumar Gala sw = in_8(&PIXIS_SW(5)); 183e02aea61SKumar Gala for (i = 0; i < 3; i++) { 184e02aea61SKumar Gala unsigned int clock = (sw >> (6 - (2 * i))) & 3; 185e02aea61SKumar Gala switch (clock) { 186e02aea61SKumar Gala case 0: 187e02aea61SKumar Gala actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 188e02aea61SKumar Gala break; 189e02aea61SKumar Gala case 1: 190e02aea61SKumar Gala actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 191e02aea61SKumar Gala break; 192e02aea61SKumar Gala case 2: 193e02aea61SKumar Gala actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; 194e02aea61SKumar Gala break; 195e02aea61SKumar Gala default: 196e02aea61SKumar Gala printf("Warning: SDREFCLK%u switch setting of '11' is " 197e02aea61SKumar Gala "unsupported\n", i + 1); 198e02aea61SKumar Gala break; 199e02aea61SKumar Gala } 200e02aea61SKumar Gala } 201e02aea61SKumar Gala #else 202d1712369SKumar Gala /* Warn if the expected SERDES reference clocks don't match the 203d1712369SKumar Gala * actual reference clocks. This needs to be done after calling 204d1712369SKumar Gala * p4080_erratum_serdes8(), since that function may modify the clocks. 205d1712369SKumar Gala */ 206e02aea61SKumar Gala sw = in_8(&PIXIS_SW(3)); 207e02aea61SKumar Gala actual[0] = (sw & 0x40) ? 208d1712369SKumar Gala SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; 209e02aea61SKumar Gala actual[1] = (sw & 0x20) ? 210d1712369SKumar Gala SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 211e02aea61SKumar Gala actual[2] = (sw & 0x10) ? 212d1712369SKumar Gala SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 213e02aea61SKumar Gala #endif 214d1712369SKumar Gala 215d1712369SKumar Gala for (i = 0; i < NUM_SRDS_BANKS; i++) { 216d1712369SKumar Gala u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 217d1712369SKumar Gala if (expected != actual[i]) { 218d1712369SKumar Gala printf("Warning: SERDES bank %u expects reference clock" 219d1712369SKumar Gala " %sMHz, but actual is %sMHz\n", i + 1, 220d1712369SKumar Gala serdes_clock_to_string(expected), 221d1712369SKumar Gala serdes_clock_to_string(actual[i])); 222d1712369SKumar Gala } 223d1712369SKumar Gala } 224d1712369SKumar Gala 225d1712369SKumar Gala return 0; 226d1712369SKumar Gala } 227d1712369SKumar Gala 228d1712369SKumar Gala void ft_board_setup(void *blob, bd_t *bd) 229d1712369SKumar Gala { 230d1712369SKumar Gala phys_addr_t base; 231d1712369SKumar Gala phys_size_t size; 232d1712369SKumar Gala 233d1712369SKumar Gala ft_cpu_setup(blob, bd); 234d1712369SKumar Gala 235d1712369SKumar Gala base = getenv_bootm_low(); 236d1712369SKumar Gala size = getenv_bootm_size(); 237d1712369SKumar Gala 238d1712369SKumar Gala fdt_fixup_memory(blob, (u64)base, (u64)size); 239d1712369SKumar Gala 240d1712369SKumar Gala #ifdef CONFIG_PCI 241d1712369SKumar Gala pci_of_setup(blob, bd); 242d1712369SKumar Gala #endif 243d1712369SKumar Gala 244d1712369SKumar Gala fdt_fixup_liodn(blob); 245a3a3e7b2SShaohui Xie fdt_fixup_dr_usb(blob, bd); 246d1712369SKumar Gala 2472915609aSAndy Fleming #ifdef CONFIG_SYS_DPAA_FMAN 2482915609aSAndy Fleming fdt_fixup_fman_ethernet(blob); 2492915609aSAndy Fleming fdt_fixup_board_enet(blob); 2502915609aSAndy Fleming #endif 251d1712369SKumar Gala } 252