1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2d1712369SKumar Gala /* 3561e710aSKumar Gala * Copyright 2009-2011 Freescale Semiconductor, Inc. 4d1712369SKumar Gala */ 5d1712369SKumar Gala 6d1712369SKumar Gala #include <common.h> 7d1712369SKumar Gala #include <command.h> 8d1712369SKumar Gala #include <netdev.h> 90e159024SLian Minghuan #include <linux/compiler.h> 10d1712369SKumar Gala #include <asm/mmu.h> 11d1712369SKumar Gala #include <asm/processor.h> 12d1712369SKumar Gala #include <asm/cache.h> 13d1712369SKumar Gala #include <asm/immap_85xx.h> 14d1712369SKumar Gala #include <asm/fsl_law.h> 15d1712369SKumar Gala #include <asm/fsl_serdes.h> 16d1712369SKumar Gala #include <asm/fsl_liodn.h> 172915609aSAndy Fleming #include <fm_eth.h> 18d1712369SKumar Gala 19d1712369SKumar Gala #include "../common/ngpixis.h" 202915609aSAndy Fleming #include "corenet_ds.h" 21d1712369SKumar Gala 22d1712369SKumar Gala DECLARE_GLOBAL_DATA_PTR; 23d1712369SKumar Gala 24d1712369SKumar Gala int checkboard (void) 25d1712369SKumar Gala { 26d1712369SKumar Gala u8 sw; 2767ac13b1SSimon Glass struct cpu_type *cpu = gd->arch.cpu; 283b83649dSYork Sun #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ 29161b4724SYork Sun defined(CONFIG_TARGET_P5040DS) 3046299078STimur Tabi unsigned int i; 31f165bc35SYork Sun #endif 32d31e53b4STimur Tabi static const char * const freq[] = {"100", "125", "156.25", "212.5" }; 33d1712369SKumar Gala 34d1712369SKumar Gala printf("Board: %sDS, ", cpu->name); 35d1712369SKumar Gala printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 36d1712369SKumar Gala in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); 37d1712369SKumar Gala 38d1712369SKumar Gala sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); 39d1712369SKumar Gala sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; 40d1712369SKumar Gala 41d1712369SKumar Gala if (sw < 0x8) 42d1712369SKumar Gala printf("vBank: %d\n", sw); 43d1712369SKumar Gala else if (sw == 0x8) 44d1712369SKumar Gala puts("Promjet\n"); 45d1712369SKumar Gala else if (sw == 0x9) 46d1712369SKumar Gala puts("NAND\n"); 47d1712369SKumar Gala else 48d1712369SKumar Gala printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); 49d1712369SKumar Gala 50d1712369SKumar Gala /* Display the actual SERDES reference clocks as configured by the 51d1712369SKumar Gala * dip switches on the board. Note that the SWx registers could 52d1712369SKumar Gala * technically be set to force the reference clocks to match the 53d1712369SKumar Gala * values that the SERDES expects (or vice versa). For now, however, 54d1712369SKumar Gala * we just display both values and hope the user notices when they 55d1712369SKumar Gala * don't match. 56d1712369SKumar Gala */ 57d1712369SKumar Gala puts("SERDES Reference Clocks: "); 58161b4724SYork Sun #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ 59161b4724SYork Sun defined(CONFIG_TARGET_P5040DS) 60e02aea61SKumar Gala sw = in_8(&PIXIS_SW(5)); 61e02aea61SKumar Gala for (i = 0; i < 3; i++) { 62e02aea61SKumar Gala unsigned int clock = (sw >> (6 - (2 * i))) & 3; 63e02aea61SKumar Gala 64e02aea61SKumar Gala printf("Bank%u=%sMhz ", i+1, freq[clock]); 65e02aea61SKumar Gala } 66161b4724SYork Sun #ifdef CONFIG_TARGET_P5040DS 67d31e53b4STimur Tabi /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ 68d31e53b4STimur Tabi sw = in_8(&PIXIS_SW(9)); 69d31e53b4STimur Tabi printf("Bank4=%sMhz ", freq[sw & 3]); 70d31e53b4STimur Tabi #endif 71e02aea61SKumar Gala puts("\n"); 72e02aea61SKumar Gala #else 73d1712369SKumar Gala sw = in_8(&PIXIS_SW(3)); 74d31e53b4STimur Tabi /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ 75d31e53b4STimur Tabi /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ 76d31e53b4STimur Tabi /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ 77d31e53b4STimur Tabi printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]); 78d31e53b4STimur Tabi printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]); 79d31e53b4STimur Tabi printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]); 80e02aea61SKumar Gala #endif 81d1712369SKumar Gala 82d1712369SKumar Gala return 0; 83d1712369SKumar Gala } 84d1712369SKumar Gala 85d1712369SKumar Gala int board_early_init_f(void) 86d1712369SKumar Gala { 87d1712369SKumar Gala volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 88d1712369SKumar Gala 89d1712369SKumar Gala /* 90d1712369SKumar Gala * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3 91d1712369SKumar Gala * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce 92d1712369SKumar Gala * the noise introduced by these unterminated and unused clock pairs. 93d1712369SKumar Gala */ 94d1712369SKumar Gala setbits_be32(&gur->ddrclkdr, 0x001B001B); 95d1712369SKumar Gala 96d1712369SKumar Gala return 0; 97d1712369SKumar Gala } 98d1712369SKumar Gala 99d1712369SKumar Gala int board_early_init_r(void) 100d1712369SKumar Gala { 101d1712369SKumar Gala const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 1029d045682SYork Sun int flash_esel = find_tlb_idx((void *)flashbase, 1); 103d1712369SKumar Gala 104d1712369SKumar Gala /* 105d1712369SKumar Gala * Remap Boot flash + PROMJET region to caching-inhibited 106d1712369SKumar Gala * so that flash can be erased properly. 107d1712369SKumar Gala */ 108d1712369SKumar Gala 109d1712369SKumar Gala /* Flush d-cache and invalidate i-cache of any FLASH data */ 110d1712369SKumar Gala flush_dcache(); 111d1712369SKumar Gala invalidate_icache(); 112d1712369SKumar Gala 1139d045682SYork Sun if (flash_esel == -1) { 1149d045682SYork Sun /* very unlikely unless something is messed up */ 1159d045682SYork Sun puts("Error: Could not find TLB for FLASH BASE\n"); 1169d045682SYork Sun flash_esel = 2; /* give our best effort to continue */ 1179d045682SYork Sun } else { 118d1712369SKumar Gala /* invalidate existing TLB entry for flash + promjet */ 119d1712369SKumar Gala disable_tlb(flash_esel); 1209d045682SYork Sun } 121d1712369SKumar Gala 122d1712369SKumar Gala set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 123d1712369SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 124d1712369SKumar Gala 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 125d1712369SKumar Gala 126d1712369SKumar Gala return 0; 127d1712369SKumar Gala } 128d1712369SKumar Gala 129d1712369SKumar Gala #define NUM_SRDS_BANKS 3 130d1712369SKumar Gala 131d1712369SKumar Gala int misc_init_r(void) 132d1712369SKumar Gala { 133d1712369SKumar Gala serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 134d1712369SKumar Gala u32 actual[NUM_SRDS_BANKS]; 135d1712369SKumar Gala unsigned int i; 136e02aea61SKumar Gala u8 sw; 137d1712369SKumar Gala 138161b4724SYork Sun #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ 139161b4724SYork Sun defined(CONFIG_TARGET_P5040DS) 140e02aea61SKumar Gala sw = in_8(&PIXIS_SW(5)); 141e02aea61SKumar Gala for (i = 0; i < 3; i++) { 142e02aea61SKumar Gala unsigned int clock = (sw >> (6 - (2 * i))) & 3; 143e02aea61SKumar Gala switch (clock) { 144e02aea61SKumar Gala case 0: 145e02aea61SKumar Gala actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 146e02aea61SKumar Gala break; 147e02aea61SKumar Gala case 1: 148e02aea61SKumar Gala actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 149e02aea61SKumar Gala break; 150e02aea61SKumar Gala case 2: 151e02aea61SKumar Gala actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; 152e02aea61SKumar Gala break; 153e02aea61SKumar Gala default: 154e02aea61SKumar Gala printf("Warning: SDREFCLK%u switch setting of '11' is " 155e02aea61SKumar Gala "unsupported\n", i + 1); 156e02aea61SKumar Gala break; 157e02aea61SKumar Gala } 158e02aea61SKumar Gala } 159e02aea61SKumar Gala #else 160d1712369SKumar Gala /* Warn if the expected SERDES reference clocks don't match the 161d1712369SKumar Gala * actual reference clocks. This needs to be done after calling 162d1712369SKumar Gala * p4080_erratum_serdes8(), since that function may modify the clocks. 163d1712369SKumar Gala */ 164e02aea61SKumar Gala sw = in_8(&PIXIS_SW(3)); 165e02aea61SKumar Gala actual[0] = (sw & 0x40) ? 166d1712369SKumar Gala SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; 167e02aea61SKumar Gala actual[1] = (sw & 0x20) ? 168d1712369SKumar Gala SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 169e02aea61SKumar Gala actual[2] = (sw & 0x10) ? 170d1712369SKumar Gala SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 171e02aea61SKumar Gala #endif 172d1712369SKumar Gala 173d1712369SKumar Gala for (i = 0; i < NUM_SRDS_BANKS; i++) { 174d1712369SKumar Gala u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 175d1712369SKumar Gala if (expected != actual[i]) { 176d1712369SKumar Gala printf("Warning: SERDES bank %u expects reference clock" 177d1712369SKumar Gala " %sMHz, but actual is %sMHz\n", i + 1, 178d1712369SKumar Gala serdes_clock_to_string(expected), 179d1712369SKumar Gala serdes_clock_to_string(actual[i])); 180d1712369SKumar Gala } 181d1712369SKumar Gala } 182d1712369SKumar Gala 183d1712369SKumar Gala return 0; 184d1712369SKumar Gala } 185d1712369SKumar Gala 186e895a4b0SSimon Glass int ft_board_setup(void *blob, bd_t *bd) 187d1712369SKumar Gala { 188d1712369SKumar Gala phys_addr_t base; 189d1712369SKumar Gala phys_size_t size; 190d1712369SKumar Gala 191d1712369SKumar Gala ft_cpu_setup(blob, bd); 192d1712369SKumar Gala 193723806ccSSimon Glass base = env_get_bootm_low(); 194723806ccSSimon Glass size = env_get_bootm_size(); 195d1712369SKumar Gala 196d1712369SKumar Gala fdt_fixup_memory(blob, (u64)base, (u64)size); 197d1712369SKumar Gala 198d1712369SKumar Gala #ifdef CONFIG_PCI 199d1712369SKumar Gala pci_of_setup(blob, bd); 200d1712369SKumar Gala #endif 201d1712369SKumar Gala 202d1712369SKumar Gala fdt_fixup_liodn(blob); 203a5c289b9SSriram Dash fsl_fdt_fixup_dr_usb(blob, bd); 204d1712369SKumar Gala 2052915609aSAndy Fleming #ifdef CONFIG_SYS_DPAA_FMAN 2062915609aSAndy Fleming fdt_fixup_fman_ethernet(blob); 2072915609aSAndy Fleming fdt_fixup_board_enet(blob); 2082915609aSAndy Fleming #endif 209e895a4b0SSimon Glass 210e895a4b0SSimon Glass return 0; 211d1712369SKumar Gala } 212