1d1712369SKumar Gala /* 2561e710aSKumar Gala * Copyright 2009-2011 Freescale Semiconductor, Inc. 3d1712369SKumar Gala * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5d1712369SKumar Gala */ 6d1712369SKumar Gala 7d1712369SKumar Gala #include <common.h> 8d1712369SKumar Gala #include <command.h> 9d1712369SKumar Gala #include <netdev.h> 100e159024SLian Minghuan #include <linux/compiler.h> 11d1712369SKumar Gala #include <asm/mmu.h> 12d1712369SKumar Gala #include <asm/processor.h> 13d1712369SKumar Gala #include <asm/cache.h> 14d1712369SKumar Gala #include <asm/immap_85xx.h> 15d1712369SKumar Gala #include <asm/fsl_law.h> 16d1712369SKumar Gala #include <asm/fsl_serdes.h> 17d1712369SKumar Gala #include <asm/fsl_liodn.h> 182915609aSAndy Fleming #include <fm_eth.h> 19d1712369SKumar Gala 20d1712369SKumar Gala #include "../common/ngpixis.h" 212915609aSAndy Fleming #include "corenet_ds.h" 22d1712369SKumar Gala 23d1712369SKumar Gala DECLARE_GLOBAL_DATA_PTR; 24d1712369SKumar Gala 25d1712369SKumar Gala int checkboard (void) 26d1712369SKumar Gala { 27d1712369SKumar Gala u8 sw; 2867ac13b1SSimon Glass struct cpu_type *cpu = gd->arch.cpu; 29*3b83649dSYork Sun #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ 30f165bc35SYork Sun defined(CONFIG_P5040DS) 3146299078STimur Tabi unsigned int i; 32f165bc35SYork Sun #endif 33d31e53b4STimur Tabi static const char * const freq[] = {"100", "125", "156.25", "212.5" }; 34d1712369SKumar Gala 35d1712369SKumar Gala printf("Board: %sDS, ", cpu->name); 36d1712369SKumar Gala printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 37d1712369SKumar Gala in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); 38d1712369SKumar Gala 39d1712369SKumar Gala sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); 40d1712369SKumar Gala sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; 41d1712369SKumar Gala 42d1712369SKumar Gala if (sw < 0x8) 43d1712369SKumar Gala printf("vBank: %d\n", sw); 44d1712369SKumar Gala else if (sw == 0x8) 45d1712369SKumar Gala puts("Promjet\n"); 46d1712369SKumar Gala else if (sw == 0x9) 47d1712369SKumar Gala puts("NAND\n"); 48d1712369SKumar Gala else 49d1712369SKumar Gala printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); 50d1712369SKumar Gala 51d1712369SKumar Gala /* Display the actual SERDES reference clocks as configured by the 52d1712369SKumar Gala * dip switches on the board. Note that the SWx registers could 53d1712369SKumar Gala * technically be set to force the reference clocks to match the 54d1712369SKumar Gala * values that the SERDES expects (or vice versa). For now, however, 55d1712369SKumar Gala * we just display both values and hope the user notices when they 56d1712369SKumar Gala * don't match. 57d1712369SKumar Gala */ 58d1712369SKumar Gala puts("SERDES Reference Clocks: "); 59*3b83649dSYork Sun #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) \ 60d31e53b4STimur Tabi || defined(CONFIG_P5040DS) 61e02aea61SKumar Gala sw = in_8(&PIXIS_SW(5)); 62e02aea61SKumar Gala for (i = 0; i < 3; i++) { 63e02aea61SKumar Gala unsigned int clock = (sw >> (6 - (2 * i))) & 3; 64e02aea61SKumar Gala 65e02aea61SKumar Gala printf("Bank%u=%sMhz ", i+1, freq[clock]); 66e02aea61SKumar Gala } 67d31e53b4STimur Tabi #ifdef CONFIG_P5040DS 68d31e53b4STimur Tabi /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ 69d31e53b4STimur Tabi sw = in_8(&PIXIS_SW(9)); 70d31e53b4STimur Tabi printf("Bank4=%sMhz ", freq[sw & 3]); 71d31e53b4STimur Tabi #endif 72e02aea61SKumar Gala puts("\n"); 73e02aea61SKumar Gala #else 74d1712369SKumar Gala sw = in_8(&PIXIS_SW(3)); 75d31e53b4STimur Tabi /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ 76d31e53b4STimur Tabi /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ 77d31e53b4STimur Tabi /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ 78d31e53b4STimur Tabi printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]); 79d31e53b4STimur Tabi printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]); 80d31e53b4STimur Tabi printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]); 81e02aea61SKumar Gala #endif 82d1712369SKumar Gala 83d1712369SKumar Gala return 0; 84d1712369SKumar Gala } 85d1712369SKumar Gala 86d1712369SKumar Gala int board_early_init_f(void) 87d1712369SKumar Gala { 88d1712369SKumar Gala volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 89d1712369SKumar Gala 90d1712369SKumar Gala /* 91d1712369SKumar Gala * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3 92d1712369SKumar Gala * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce 93d1712369SKumar Gala * the noise introduced by these unterminated and unused clock pairs. 94d1712369SKumar Gala */ 95d1712369SKumar Gala setbits_be32(&gur->ddrclkdr, 0x001B001B); 96d1712369SKumar Gala 97d1712369SKumar Gala return 0; 98d1712369SKumar Gala } 99d1712369SKumar Gala 100d1712369SKumar Gala int board_early_init_r(void) 101d1712369SKumar Gala { 102d1712369SKumar Gala const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 1039d045682SYork Sun int flash_esel = find_tlb_idx((void *)flashbase, 1); 104d1712369SKumar Gala 105d1712369SKumar Gala /* 106d1712369SKumar Gala * Remap Boot flash + PROMJET region to caching-inhibited 107d1712369SKumar Gala * so that flash can be erased properly. 108d1712369SKumar Gala */ 109d1712369SKumar Gala 110d1712369SKumar Gala /* Flush d-cache and invalidate i-cache of any FLASH data */ 111d1712369SKumar Gala flush_dcache(); 112d1712369SKumar Gala invalidate_icache(); 113d1712369SKumar Gala 1149d045682SYork Sun if (flash_esel == -1) { 1159d045682SYork Sun /* very unlikely unless something is messed up */ 1169d045682SYork Sun puts("Error: Could not find TLB for FLASH BASE\n"); 1179d045682SYork Sun flash_esel = 2; /* give our best effort to continue */ 1189d045682SYork Sun } else { 119d1712369SKumar Gala /* invalidate existing TLB entry for flash + promjet */ 120d1712369SKumar Gala disable_tlb(flash_esel); 1219d045682SYork Sun } 122d1712369SKumar Gala 123d1712369SKumar Gala set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 124d1712369SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 125d1712369SKumar Gala 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 126d1712369SKumar Gala 127d1712369SKumar Gala return 0; 128d1712369SKumar Gala } 129d1712369SKumar Gala 130d1712369SKumar Gala #define NUM_SRDS_BANKS 3 131d1712369SKumar Gala 132d1712369SKumar Gala int misc_init_r(void) 133d1712369SKumar Gala { 134d1712369SKumar Gala serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 135d1712369SKumar Gala u32 actual[NUM_SRDS_BANKS]; 136d1712369SKumar Gala unsigned int i; 137e02aea61SKumar Gala u8 sw; 138d1712369SKumar Gala 139*3b83649dSYork Sun #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) \ 140d31e53b4STimur Tabi || defined(CONFIG_P5040DS) 141e02aea61SKumar Gala sw = in_8(&PIXIS_SW(5)); 142e02aea61SKumar Gala for (i = 0; i < 3; i++) { 143e02aea61SKumar Gala unsigned int clock = (sw >> (6 - (2 * i))) & 3; 144e02aea61SKumar Gala switch (clock) { 145e02aea61SKumar Gala case 0: 146e02aea61SKumar Gala actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 147e02aea61SKumar Gala break; 148e02aea61SKumar Gala case 1: 149e02aea61SKumar Gala actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 150e02aea61SKumar Gala break; 151e02aea61SKumar Gala case 2: 152e02aea61SKumar Gala actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; 153e02aea61SKumar Gala break; 154e02aea61SKumar Gala default: 155e02aea61SKumar Gala printf("Warning: SDREFCLK%u switch setting of '11' is " 156e02aea61SKumar Gala "unsupported\n", i + 1); 157e02aea61SKumar Gala break; 158e02aea61SKumar Gala } 159e02aea61SKumar Gala } 160e02aea61SKumar Gala #else 161d1712369SKumar Gala /* Warn if the expected SERDES reference clocks don't match the 162d1712369SKumar Gala * actual reference clocks. This needs to be done after calling 163d1712369SKumar Gala * p4080_erratum_serdes8(), since that function may modify the clocks. 164d1712369SKumar Gala */ 165e02aea61SKumar Gala sw = in_8(&PIXIS_SW(3)); 166e02aea61SKumar Gala actual[0] = (sw & 0x40) ? 167d1712369SKumar Gala SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; 168e02aea61SKumar Gala actual[1] = (sw & 0x20) ? 169d1712369SKumar Gala SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 170e02aea61SKumar Gala actual[2] = (sw & 0x10) ? 171d1712369SKumar Gala SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 172e02aea61SKumar Gala #endif 173d1712369SKumar Gala 174d1712369SKumar Gala for (i = 0; i < NUM_SRDS_BANKS; i++) { 175d1712369SKumar Gala u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 176d1712369SKumar Gala if (expected != actual[i]) { 177d1712369SKumar Gala printf("Warning: SERDES bank %u expects reference clock" 178d1712369SKumar Gala " %sMHz, but actual is %sMHz\n", i + 1, 179d1712369SKumar Gala serdes_clock_to_string(expected), 180d1712369SKumar Gala serdes_clock_to_string(actual[i])); 181d1712369SKumar Gala } 182d1712369SKumar Gala } 183d1712369SKumar Gala 184d1712369SKumar Gala return 0; 185d1712369SKumar Gala } 186d1712369SKumar Gala 187e895a4b0SSimon Glass int ft_board_setup(void *blob, bd_t *bd) 188d1712369SKumar Gala { 189d1712369SKumar Gala phys_addr_t base; 190d1712369SKumar Gala phys_size_t size; 191d1712369SKumar Gala 192d1712369SKumar Gala ft_cpu_setup(blob, bd); 193d1712369SKumar Gala 194d1712369SKumar Gala base = getenv_bootm_low(); 195d1712369SKumar Gala size = getenv_bootm_size(); 196d1712369SKumar Gala 197d1712369SKumar Gala fdt_fixup_memory(blob, (u64)base, (u64)size); 198d1712369SKumar Gala 199d1712369SKumar Gala #ifdef CONFIG_PCI 200d1712369SKumar Gala pci_of_setup(blob, bd); 201d1712369SKumar Gala #endif 202d1712369SKumar Gala 203d1712369SKumar Gala fdt_fixup_liodn(blob); 204a5c289b9SSriram Dash fsl_fdt_fixup_dr_usb(blob, bd); 205d1712369SKumar Gala 2062915609aSAndy Fleming #ifdef CONFIG_SYS_DPAA_FMAN 2072915609aSAndy Fleming fdt_fixup_fman_ethernet(blob); 2082915609aSAndy Fleming fdt_fixup_board_enet(blob); 2092915609aSAndy Fleming #endif 210e895a4b0SSimon Glass 211e895a4b0SSimon Glass return 0; 212d1712369SKumar Gala } 213