1d1712369SKumar Gala /* 2d1712369SKumar Gala * Copyright 2009-2010 Freescale Semiconductor, Inc. 3d1712369SKumar Gala * 4d1712369SKumar Gala * See file CREDITS for list of people who contributed to this 5d1712369SKumar Gala * project. 6d1712369SKumar Gala * 7d1712369SKumar Gala * This program is free software; you can redistribute it and/or 8d1712369SKumar Gala * modify it under the terms of the GNU General Public License as 9d1712369SKumar Gala * published by the Free Software Foundation; either version 2 of 10d1712369SKumar Gala * the License, or (at your option) any later version. 11d1712369SKumar Gala * 12d1712369SKumar Gala * This program is distributed in the hope that it will be useful, 13d1712369SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 14d1712369SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15d1712369SKumar Gala * GNU General Public License for more details. 16d1712369SKumar Gala * 17d1712369SKumar Gala * You should have received a copy of the GNU General Public License 18d1712369SKumar Gala * along with this program; if not, write to the Free Software 19d1712369SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20d1712369SKumar Gala * MA 02111-1307 USA 21d1712369SKumar Gala */ 22d1712369SKumar Gala 23d1712369SKumar Gala #include <common.h> 24d1712369SKumar Gala #include <command.h> 25d1712369SKumar Gala #include <netdev.h> 26*0e159024SLian Minghuan #include <linux/compiler.h> 27d1712369SKumar Gala #include <asm/mmu.h> 28d1712369SKumar Gala #include <asm/processor.h> 29d1712369SKumar Gala #include <asm/cache.h> 30d1712369SKumar Gala #include <asm/immap_85xx.h> 31d1712369SKumar Gala #include <asm/fsl_law.h> 32d1712369SKumar Gala #include <asm/fsl_ddr_sdram.h> 33d1712369SKumar Gala #include <asm/fsl_serdes.h> 34d1712369SKumar Gala #include <asm/fsl_portals.h> 35d1712369SKumar Gala #include <asm/fsl_liodn.h> 36d1712369SKumar Gala 37d1712369SKumar Gala extern void pci_of_setup(void *blob, bd_t *bd); 38d1712369SKumar Gala 39d1712369SKumar Gala #include "../common/ngpixis.h" 40d1712369SKumar Gala 41d1712369SKumar Gala DECLARE_GLOBAL_DATA_PTR; 42d1712369SKumar Gala 43d1712369SKumar Gala void cpu_mp_lmb_reserve(struct lmb *lmb); 44d1712369SKumar Gala 45d1712369SKumar Gala int checkboard (void) 46d1712369SKumar Gala { 47d1712369SKumar Gala u8 sw; 48d1712369SKumar Gala struct cpu_type *cpu = gd->cpu; 49d1712369SKumar Gala 50d1712369SKumar Gala printf("Board: %sDS, ", cpu->name); 51d1712369SKumar Gala printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 52d1712369SKumar Gala in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); 53d1712369SKumar Gala 54d1712369SKumar Gala sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); 55d1712369SKumar Gala sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; 56d1712369SKumar Gala 57d1712369SKumar Gala if (sw < 0x8) 58d1712369SKumar Gala printf("vBank: %d\n", sw); 59d1712369SKumar Gala else if (sw == 0x8) 60d1712369SKumar Gala puts("Promjet\n"); 61d1712369SKumar Gala else if (sw == 0x9) 62d1712369SKumar Gala puts("NAND\n"); 63d1712369SKumar Gala else 64d1712369SKumar Gala printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); 65d1712369SKumar Gala 66d1712369SKumar Gala #ifdef CONFIG_PHYS_64BIT 67d1712369SKumar Gala puts("36-bit Addressing\n"); 68d1712369SKumar Gala #endif 69d1712369SKumar Gala 70d1712369SKumar Gala /* Display the actual SERDES reference clocks as configured by the 71d1712369SKumar Gala * dip switches on the board. Note that the SWx registers could 72d1712369SKumar Gala * technically be set to force the reference clocks to match the 73d1712369SKumar Gala * values that the SERDES expects (or vice versa). For now, however, 74d1712369SKumar Gala * we just display both values and hope the user notices when they 75d1712369SKumar Gala * don't match. 76d1712369SKumar Gala */ 77d1712369SKumar Gala puts("SERDES Reference Clocks: "); 78d1712369SKumar Gala sw = in_8(&PIXIS_SW(3)); 79d1712369SKumar Gala printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100); 80d1712369SKumar Gala printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125"); 81d1712369SKumar Gala printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125"); 82d1712369SKumar Gala 83d1712369SKumar Gala return 0; 84d1712369SKumar Gala } 85d1712369SKumar Gala 86d1712369SKumar Gala int board_early_init_f(void) 87d1712369SKumar Gala { 88d1712369SKumar Gala volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 89d1712369SKumar Gala 90d1712369SKumar Gala /* 91d1712369SKumar Gala * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3 92d1712369SKumar Gala * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce 93d1712369SKumar Gala * the noise introduced by these unterminated and unused clock pairs. 94d1712369SKumar Gala */ 95d1712369SKumar Gala setbits_be32(&gur->ddrclkdr, 0x001B001B); 96d1712369SKumar Gala 97d1712369SKumar Gala return 0; 98d1712369SKumar Gala } 99d1712369SKumar Gala 100d1712369SKumar Gala int board_early_init_r(void) 101d1712369SKumar Gala { 102d1712369SKumar Gala const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 103d1712369SKumar Gala const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 104d1712369SKumar Gala 105d1712369SKumar Gala /* 106d1712369SKumar Gala * Remap Boot flash + PROMJET region to caching-inhibited 107d1712369SKumar Gala * so that flash can be erased properly. 108d1712369SKumar Gala */ 109d1712369SKumar Gala 110d1712369SKumar Gala /* Flush d-cache and invalidate i-cache of any FLASH data */ 111d1712369SKumar Gala flush_dcache(); 112d1712369SKumar Gala invalidate_icache(); 113d1712369SKumar Gala 114d1712369SKumar Gala /* invalidate existing TLB entry for flash + promjet */ 115d1712369SKumar Gala disable_tlb(flash_esel); 116d1712369SKumar Gala 117d1712369SKumar Gala set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 118d1712369SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 119d1712369SKumar Gala 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 120d1712369SKumar Gala 121d1712369SKumar Gala set_liodns(); 122d1712369SKumar Gala setup_portals(); 123d1712369SKumar Gala 124d1712369SKumar Gala return 0; 125d1712369SKumar Gala } 126d1712369SKumar Gala 127d1712369SKumar Gala static const char *serdes_clock_to_string(u32 clock) 128d1712369SKumar Gala { 129d1712369SKumar Gala switch(clock) { 130d1712369SKumar Gala case SRDS_PLLCR0_RFCK_SEL_100: 131d1712369SKumar Gala return "100"; 132d1712369SKumar Gala case SRDS_PLLCR0_RFCK_SEL_125: 133d1712369SKumar Gala return "125"; 134d1712369SKumar Gala case SRDS_PLLCR0_RFCK_SEL_156_25: 135d1712369SKumar Gala return "156.25"; 136d1712369SKumar Gala default: 137d1712369SKumar Gala return "???"; 138d1712369SKumar Gala } 139d1712369SKumar Gala } 140d1712369SKumar Gala 141d1712369SKumar Gala #define NUM_SRDS_BANKS 3 142d1712369SKumar Gala 143d1712369SKumar Gala int misc_init_r(void) 144d1712369SKumar Gala { 145d1712369SKumar Gala serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 146*0e159024SLian Minghuan __maybe_unused ccsr_gur_t *gur; 147d1712369SKumar Gala u32 actual[NUM_SRDS_BANKS]; 148d1712369SKumar Gala unsigned int i; 149d1712369SKumar Gala u8 sw3; 150d1712369SKumar Gala 151*0e159024SLian Minghuan gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 152*0e159024SLian Minghuan #ifdef CONFIG_SRIO1 153*0e159024SLian Minghuan if (is_serdes_configured(SRIO1)) { 154*0e159024SLian Minghuan set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, 155*0e159024SLian Minghuan LAW_TRGT_IF_RIO_1); 156*0e159024SLian Minghuan } else { 157*0e159024SLian Minghuan printf (" SRIO1: disabled\n"); 158*0e159024SLian Minghuan } 159*0e159024SLian Minghuan #else 160*0e159024SLian Minghuan setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ 161*0e159024SLian Minghuan #endif 162*0e159024SLian Minghuan 163*0e159024SLian Minghuan #ifdef CONFIG_SRIO2 164*0e159024SLian Minghuan if (is_serdes_configured(SRIO2)) { 165*0e159024SLian Minghuan set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, 166*0e159024SLian Minghuan LAW_TRGT_IF_RIO_2); 167*0e159024SLian Minghuan } else { 168*0e159024SLian Minghuan printf (" SRIO2: disabled\n"); 169*0e159024SLian Minghuan } 170*0e159024SLian Minghuan #else 171*0e159024SLian Minghuan setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ 172*0e159024SLian Minghuan #endif 173*0e159024SLian Minghuan 174d1712369SKumar Gala /* Warn if the expected SERDES reference clocks don't match the 175d1712369SKumar Gala * actual reference clocks. This needs to be done after calling 176d1712369SKumar Gala * p4080_erratum_serdes8(), since that function may modify the clocks. 177d1712369SKumar Gala */ 178d1712369SKumar Gala sw3 = in_8(&PIXIS_SW(3)); 179d1712369SKumar Gala actual[0] = (sw3 & 0x40) ? 180d1712369SKumar Gala SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; 181d1712369SKumar Gala actual[1] = (sw3 & 0x20) ? 182d1712369SKumar Gala SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 183d1712369SKumar Gala actual[2] = (sw3 & 0x10) ? 184d1712369SKumar Gala SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; 185d1712369SKumar Gala 186d1712369SKumar Gala for (i = 0; i < NUM_SRDS_BANKS; i++) { 187d1712369SKumar Gala u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 188d1712369SKumar Gala if (expected != actual[i]) { 189d1712369SKumar Gala printf("Warning: SERDES bank %u expects reference clock" 190d1712369SKumar Gala " %sMHz, but actual is %sMHz\n", i + 1, 191d1712369SKumar Gala serdes_clock_to_string(expected), 192d1712369SKumar Gala serdes_clock_to_string(actual[i])); 193d1712369SKumar Gala } 194d1712369SKumar Gala } 195d1712369SKumar Gala 196d1712369SKumar Gala return 0; 197d1712369SKumar Gala } 198d1712369SKumar Gala 199d1712369SKumar Gala phys_size_t initdram(int board_type) 200d1712369SKumar Gala { 201d1712369SKumar Gala phys_size_t dram_size; 202d1712369SKumar Gala 203d1712369SKumar Gala puts("Initializing....\n"); 204d1712369SKumar Gala 205d1712369SKumar Gala dram_size = fsl_ddr_sdram(); 206d1712369SKumar Gala 207d1712369SKumar Gala setup_ddr_tlbs(dram_size / 0x100000); 208d1712369SKumar Gala 209d1712369SKumar Gala puts(" DDR: "); 210d1712369SKumar Gala return dram_size; 211d1712369SKumar Gala } 212d1712369SKumar Gala 213d1712369SKumar Gala #ifdef CONFIG_MP 214d1712369SKumar Gala void board_lmb_reserve(struct lmb *lmb) 215d1712369SKumar Gala { 216d1712369SKumar Gala cpu_mp_lmb_reserve(lmb); 217d1712369SKumar Gala } 218d1712369SKumar Gala #endif 219d1712369SKumar Gala 220d1712369SKumar Gala void ft_srio_setup(void *blob) 221d1712369SKumar Gala { 222d1712369SKumar Gala #ifdef CONFIG_SRIO1 223d1712369SKumar Gala if (!is_serdes_configured(SRIO1)) { 224d1712369SKumar Gala fdt_del_node_and_alias(blob, "rio0"); 225d1712369SKumar Gala } 226d1712369SKumar Gala #else 227d1712369SKumar Gala fdt_del_node_and_alias(blob, "rio0"); 228d1712369SKumar Gala #endif 229d1712369SKumar Gala #ifdef CONFIG_SRIO2 230d1712369SKumar Gala if (!is_serdes_configured(SRIO2)) { 231d1712369SKumar Gala fdt_del_node_and_alias(blob, "rio1"); 232d1712369SKumar Gala } 233d1712369SKumar Gala #else 234d1712369SKumar Gala fdt_del_node_and_alias(blob, "rio1"); 235d1712369SKumar Gala #endif 236d1712369SKumar Gala } 237d1712369SKumar Gala 238d1712369SKumar Gala void ft_board_setup(void *blob, bd_t *bd) 239d1712369SKumar Gala { 240d1712369SKumar Gala phys_addr_t base; 241d1712369SKumar Gala phys_size_t size; 242d1712369SKumar Gala 243d1712369SKumar Gala ft_cpu_setup(blob, bd); 244d1712369SKumar Gala 245d1712369SKumar Gala ft_srio_setup(blob); 246d1712369SKumar Gala 247d1712369SKumar Gala base = getenv_bootm_low(); 248d1712369SKumar Gala size = getenv_bootm_size(); 249d1712369SKumar Gala 250d1712369SKumar Gala fdt_fixup_memory(blob, (u64)base, (u64)size); 251d1712369SKumar Gala 252d1712369SKumar Gala #ifdef CONFIG_PCI 253d1712369SKumar Gala pci_of_setup(blob, bd); 254d1712369SKumar Gala #endif 255d1712369SKumar Gala 256d1712369SKumar Gala fdt_fixup_liodn(blob); 257d1712369SKumar Gala } 258d1712369SKumar Gala 259d1712369SKumar Gala int board_eth_init(bd_t *bis) 260d1712369SKumar Gala { 261d1712369SKumar Gala return pci_eth_init(bis); 262d1712369SKumar Gala } 263