xref: /openbmc/u-boot/board/freescale/common/qixis.h (revision e91610da)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2011 Freescale Semiconductor
4  * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
5  *
6  * This file provides support for the QIXIS of some Freescale reference boards.
7  */
8 
9 #ifndef __QIXIS_H_
10 #define __QIXIS_H_
11 
12 struct qixis {
13 	u8 id;      /* ID value uniquely identifying each QDS board type */
14 	u8 arch;    /* Board version information */
15 	u8 scver;   /* QIXIS Version Register */
16 	u8 model;   /* Information of software programming model version */
17 	u8 tagdata;
18 	u8 ctl_sys;
19 	u8 aux;         /* Auxiliary Register,0x06 */
20 	u8 clk_spd;
21 	u8 stat_dut;
22 	u8 stat_sys;
23 	u8 stat_alrm;
24 	u8 present;
25 	u8 present2;    /* Presence Status Register 2,0x0c */
26 	u8 rcw_ctl;
27 	u8 ctl_led;
28 	u8 i2cblk;
29 	u8 rcfg_ctl;    /* Reconfig Control Register,0x10 */
30 	u8 rcfg_st;
31 	u8 dcm_ad;
32 	u8 dcm_da;
33 	u8 dcmd;
34 	u8 dmsg;
35 	u8 gdc;
36 	u8 gdd;         /* DCM Debug Data Register,0x17 */
37 	u8 dmack;
38 	u8 res1[6];
39 	u8 watch;       /* Watchdog Register,0x1F */
40 	u8 pwr_ctl[2];  /* Power Control Register,0x20 */
41 	u8 res2[2];
42 	u8 pwr_stat[4]; /* Power Status Register,0x24 */
43 	u8 res3[8];
44 	u8 clk_spd2[2];  /* SYSCLK clock Speed Register,0x30 */
45 	u8 res4[2];
46 	u8 sclk[3];  /* Clock Configuration Registers,0x34 */
47 	u8 res5;
48 	u8 dclk[3];
49 	u8 res6;
50 	u8 clk_dspd[3];
51 	u8 res7;
52 	u8 rst_ctl;     /* Reset Control Register,0x40 */
53 	u8 rst_stat;    /* Reset Status Register */
54 	u8 rst_rsn;     /* Reset Reason Register */
55 	u8 rst_frc[2];  /* Reset Force Registers,0x43 */
56 	u8 res8[11];
57 	u8 brdcfg[16];  /* Board Configuration Register,0x50 */
58 	u8 dutcfg[16];
59 	u8 rcw_ad[2];   /* RCW SRAM Address Registers,0x70 */
60 	u8 rcw_data;
61 	u8 res9[5];
62 	u8 post_ctl;
63 	u8 post_stat;
64 	u8 post_dat[2];
65 	u8 pi_d[4];
66 	u8 gpio_io[4];
67 	u8 gpio_dir[4];
68 	u8 res10[20];
69 	u8 rjtag_ctl;
70 	u8 rjtag_dat;
71 	u8 res11[2];
72 	u8 trig_src[4];
73 	u8 trig_dst[4];
74 	u8 trig_stat;
75 	u8 res12[3];
76 	u8 trig_ctr[4];
77 	u8 res13[16];
78 	u8 clk_freq[6];	/* Clock Measurement Registers */
79 	u8 res_c6[8];
80 	u8 clk_base[2];	/* Clock Frequency Base Reg */
81 	u8 res_d0[8];
82 	u8 cms[2];	/* Core Management Space Address Register, 0xD8 */
83 	u8 res_c0[6];
84 	u8 aux2[4];	/* Auxiliary Registers,0xE0 */
85 	u8 res14[10];
86 	u8 aux_ad;
87 	u8 aux_da;
88 	u8 res15[16];
89 };
90 
91 u8 qixis_read(unsigned int reg);
92 void qixis_write(unsigned int reg, u8 value);
93 u16 qixis_read_minor(void);
94 char *qixis_read_time(char *result);
95 char *qixis_read_tag(char *buf);
96 const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
97 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
98 u8 qixis_read_i2c(unsigned int reg);
99 void qixis_write_i2c(unsigned int reg, u8 value);
100 #endif
101 
102 #if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR)
103 #define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg))
104 #define QIXIS_WRITE(reg, value) \
105 	qixis_write_i2c(offsetof(struct qixis, reg), value)
106 #else
107 #define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
108 #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
109 #endif
110 
111 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
112 #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
113 #define QIXIS_WRITE_I2C(reg, value) \
114 			qixis_write_i2c(offsetof(struct qixis, reg), value)
115 #endif
116 
117 /* Use for SDHC adapter card type identification and operation */
118 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
119 #define QIXIS_SDID_MASK                         0x07
120 #define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45         0x1	/* eMMC Card Rev4.5 */
121 #define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY   0x2	/* SD/MMC Legacy Card */
122 #define QIXIS_ESDHC_ADAPTER_TYPE_EMMC44         0x3	/* eMMC Card Rev4.4 */
123 #define QIXIS_ESDHC_ADAPTER_TYPE_RSV            0x4	/* Reserved */
124 #define QIXIS_ESDHC_ADAPTER_TYPE_MMC            0x5	/* MMC Card */
125 #define QIXIS_ESDHC_ADAPTER_TYPE_SD             0x6	/* SD Card Rev2.0 3.0 */
126 #define QIXIS_ESDHC_NO_ADAPTER                  0x7	/* No Card is Present*/
127 
128 #define QIXIS_SDCLKIN		0x08
129 #define QIXIS_SDCLKOUT		0x02
130 #define QIXIS_DAT5_6_7		0X02
131 #define QIXIS_DAT4		0X01
132 
133 #define QIXIS_EVDD_BY_SDHC_VS	0x0c
134 #endif
135 
136 #endif
137