xref: /openbmc/u-boot/board/freescale/common/qixis.c (revision e77e65df) 
1 /*
2  * Copyright 2011 Freescale Semiconductor
3  * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  *
7  * This file provides support for the QIXIS of some Freescale reference boards.
8  */
9 
10 #include <common.h>
11 #include <command.h>
12 #include <asm/io.h>
13 #include <linux/time.h>
14 #include <i2c.h>
15 #include "qixis.h"
16 
17 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
18 u8 qixis_read_i2c(unsigned int reg)
19 {
20 	return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
21 }
22 
23 void qixis_write_i2c(unsigned int reg, u8 value)
24 {
25 	u8 val = value;
26 	i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
27 }
28 #endif
29 
30 u8 qixis_read(unsigned int reg)
31 {
32 	void *p = (void *)QIXIS_BASE;
33 
34 	return in_8(p + reg);
35 }
36 
37 void qixis_write(unsigned int reg, u8 value)
38 {
39 	void *p = (void *)QIXIS_BASE;
40 
41 	out_8(p + reg, value);
42 }
43 
44 u16 qixis_read_minor(void)
45 {
46 	u16 minor;
47 
48 	/* this data is in little endian */
49 	QIXIS_WRITE(tagdata, 5);
50 	minor = QIXIS_READ(tagdata);
51 	QIXIS_WRITE(tagdata, 6);
52 	minor += QIXIS_READ(tagdata) << 8;
53 
54 	return minor;
55 }
56 
57 char *qixis_read_time(char *result)
58 {
59 	time_t time = 0;
60 	int i;
61 
62 	/* timestamp is in 32-bit big endian */
63 	for (i = 8; i <= 11; i++) {
64 		QIXIS_WRITE(tagdata, i);
65 		time =  (time << 8) + QIXIS_READ(tagdata);
66 	}
67 
68 	return ctime_r(&time, result);
69 }
70 
71 char *qixis_read_tag(char *buf)
72 {
73 	int i;
74 	char tag, *ptr = buf;
75 
76 	for (i = 16; i <= 63; i++) {
77 		QIXIS_WRITE(tagdata, i);
78 		tag = QIXIS_READ(tagdata);
79 		*(ptr++) = tag;
80 		if (!tag)
81 			break;
82 	}
83 	if (i > 63)
84 		*ptr = '\0';
85 
86 	return buf;
87 }
88 
89 /*
90  * return the string of binary of u8 in the format of
91  * 1010 10_0. The masked bit is filled as underscore.
92  */
93 const char *byte_to_binary_mask(u8 val, u8 mask, char *buf)
94 {
95 	char *ptr;
96 	int i;
97 
98 	ptr = buf;
99 	for (i = 0x80; i > 0x08 ; i >>= 1, ptr++)
100 		*ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
101 	*(ptr++) = ' ';
102 	for (i = 0x08; i > 0 ; i >>= 1, ptr++)
103 		*ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
104 
105 	*ptr = '\0';
106 
107 	return buf;
108 }
109 
110 #ifdef QIXIS_RST_FORCE_MEM
111 void board_assert_mem_reset(void)
112 {
113 	u8 rst;
114 
115 	rst = QIXIS_READ(rst_frc[0]);
116 	if (!(rst & QIXIS_RST_FORCE_MEM))
117 		QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM);
118 }
119 
120 void board_deassert_mem_reset(void)
121 {
122 	u8 rst;
123 
124 	rst = QIXIS_READ(rst_frc[0]);
125 	if (rst & QIXIS_RST_FORCE_MEM)
126 		QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM);
127 }
128 #endif
129 
130 void qixis_reset(void)
131 {
132 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
133 }
134 
135 void qixis_bank_reset(void)
136 {
137 	QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
138 	QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
139 }
140 
141 /* Set the boot bank to the power-on default bank */
142 void clear_altbank(void)
143 {
144 	u8 reg;
145 
146 	reg = QIXIS_READ(brdcfg[0]);
147 	reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_DFLTBANK;
148 	QIXIS_WRITE(brdcfg[0], reg);
149 }
150 
151 /* Set the boot bank to the alternate bank */
152 void set_altbank(void)
153 {
154 	u8 reg;
155 
156 	reg = QIXIS_READ(brdcfg[0]);
157 	reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK;
158 	QIXIS_WRITE(brdcfg[0], reg);
159 }
160 
161 static void qixis_dump_regs(void)
162 {
163 	int i;
164 
165 	printf("id	= %02x\n", QIXIS_READ(id));
166 	printf("arch	= %02x\n", QIXIS_READ(arch));
167 	printf("scver	= %02x\n", QIXIS_READ(scver));
168 	printf("model	= %02x\n", QIXIS_READ(model));
169 	printf("rst_ctl	= %02x\n", QIXIS_READ(rst_ctl));
170 	printf("aux	= %02x\n", QIXIS_READ(aux));
171 	for (i = 0; i < 16; i++)
172 		printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i]));
173 	for (i = 0; i < 16; i++)
174 		printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i]));
175 	printf("sclk	= %02x%02x%02x\n", QIXIS_READ(sclk[0]),
176 		QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
177 	printf("dclk	= %02x%02x%02x\n", QIXIS_READ(dclk[0]),
178 		QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2]));
179 	printf("aux     = %02x\n", QIXIS_READ(aux));
180 	printf("watch	= %02x\n", QIXIS_READ(watch));
181 	printf("ctl_sys	= %02x\n", QIXIS_READ(ctl_sys));
182 	printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
183 	printf("present = %02x\n", QIXIS_READ(present));
184 	printf("present2 = %02x\n", QIXIS_READ(present2));
185 	printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
186 	printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
187 	printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
188 	printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
189 }
190 
191 static void __qixis_dump_switch(void)
192 {
193 	puts("Reverse engineering switch is not implemented for this board\n");
194 }
195 
196 void qixis_dump_switch(void)
197 	__attribute__((weak, alias("__qixis_dump_switch")));
198 
199 int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
200 {
201 	int i;
202 
203 	if (argc <= 1) {
204 		clear_altbank();
205 		qixis_reset();
206 	} else if (strcmp(argv[1], "altbank") == 0) {
207 		set_altbank();
208 		qixis_bank_reset();
209 	} else if (strcmp(argv[1], "watchdog") == 0) {
210 		static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
211 					  "1min", "2min", "4min", "8min"};
212 		u8 rcfg = QIXIS_READ(rcfg_ctl);
213 
214 		if (argv[2] == NULL) {
215 			printf("qixis watchdog <watchdog_period>\n");
216 			return 0;
217 		}
218 		for (i = 0; i < ARRAY_SIZE(period); i++) {
219 			if (strcmp(argv[2], period[i]) == 0) {
220 				/* disable watchdog */
221 				QIXIS_WRITE(rcfg_ctl,
222 					rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE);
223 				QIXIS_WRITE(watch, ((i<<2) - 1));
224 				QIXIS_WRITE(rcfg_ctl, rcfg);
225 				return 0;
226 			}
227 		}
228 	} else if (strcmp(argv[1], "dump") == 0) {
229 		qixis_dump_regs();
230 		return 0;
231 	} else if (strcmp(argv[1], "switch") == 0) {
232 		qixis_dump_switch();
233 		return 0;
234 	} else {
235 		printf("Invalid option: %s\n", argv[1]);
236 		return 1;
237 	}
238 
239 	return 0;
240 }
241 
242 U_BOOT_CMD(
243 	qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd,
244 	"Reset the board using the FPGA sequencer",
245 	"- hard reset to default bank\n"
246 	"qixis_reset altbank - reset to alternate bank\n"
247 	"qixis watchdog <watchdog_period> - set the watchdog period\n"
248 	"	period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
249 	"qixis_reset dump - display the QIXIS registers\n"
250 	"qixis_reset switch - display switch\n"
251 	);
252