1 /* 2 * Copyright 2011 Freescale Semiconductor 3 * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * This file provides support for the QIXIS of some Freescale reference boards. 8 */ 9 10 #include <common.h> 11 #include <command.h> 12 #include <asm/io.h> 13 #include <linux/time.h> 14 #include <i2c.h> 15 #include "qixis.h" 16 17 #ifdef CONFIG_SYS_I2C_FPGA_ADDR 18 u8 qixis_read_i2c(unsigned int reg) 19 { 20 return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg); 21 } 22 23 void qixis_write_i2c(unsigned int reg, u8 value) 24 { 25 u8 val = value; 26 i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val); 27 } 28 #endif 29 30 u8 qixis_read(unsigned int reg) 31 { 32 void *p = (void *)QIXIS_BASE; 33 34 return in_8(p + reg); 35 } 36 37 void qixis_write(unsigned int reg, u8 value) 38 { 39 void *p = (void *)QIXIS_BASE; 40 41 out_8(p + reg, value); 42 } 43 44 u16 qixis_read_minor(void) 45 { 46 u16 minor; 47 48 /* this data is in little endian */ 49 QIXIS_WRITE(tagdata, 5); 50 minor = QIXIS_READ(tagdata); 51 QIXIS_WRITE(tagdata, 6); 52 minor += QIXIS_READ(tagdata) << 8; 53 54 return minor; 55 } 56 57 char *qixis_read_time(char *result) 58 { 59 time_t time = 0; 60 int i; 61 62 /* timestamp is in 32-bit big endian */ 63 for (i = 8; i <= 11; i++) { 64 QIXIS_WRITE(tagdata, i); 65 time = (time << 8) + QIXIS_READ(tagdata); 66 } 67 68 return ctime_r(&time, result); 69 } 70 71 char *qixis_read_tag(char *buf) 72 { 73 int i; 74 char tag, *ptr = buf; 75 76 for (i = 16; i <= 63; i++) { 77 QIXIS_WRITE(tagdata, i); 78 tag = QIXIS_READ(tagdata); 79 *(ptr++) = tag; 80 if (!tag) 81 break; 82 } 83 if (i > 63) 84 *ptr = '\0'; 85 86 return buf; 87 } 88 89 /* 90 * return the string of binary of u8 in the format of 91 * 1010 10_0. The masked bit is filled as underscore. 92 */ 93 const char *byte_to_binary_mask(u8 val, u8 mask, char *buf) 94 { 95 char *ptr; 96 int i; 97 98 ptr = buf; 99 for (i = 0x80; i > 0x08 ; i >>= 1, ptr++) 100 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0'); 101 *(ptr++) = ' '; 102 for (i = 0x08; i > 0 ; i >>= 1, ptr++) 103 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0'); 104 105 *ptr = '\0'; 106 107 return buf; 108 } 109 110 void qixis_reset(void) 111 { 112 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); 113 } 114 115 void qixis_bank_reset(void) 116 { 117 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); 118 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); 119 } 120 121 /* Set the boot bank to the power-on default bank */ 122 void clear_altbank(void) 123 { 124 u8 reg; 125 126 reg = QIXIS_READ(brdcfg[0]); 127 reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_DFLTBANK; 128 QIXIS_WRITE(brdcfg[0], reg); 129 } 130 131 /* Set the boot bank to the alternate bank */ 132 void set_altbank(void) 133 { 134 u8 reg; 135 136 reg = QIXIS_READ(brdcfg[0]); 137 reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK; 138 QIXIS_WRITE(brdcfg[0], reg); 139 } 140 141 static void qixis_dump_regs(void) 142 { 143 int i; 144 145 printf("id = %02x\n", QIXIS_READ(id)); 146 printf("arch = %02x\n", QIXIS_READ(arch)); 147 printf("scver = %02x\n", QIXIS_READ(scver)); 148 printf("model = %02x\n", QIXIS_READ(model)); 149 printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl)); 150 printf("aux = %02x\n", QIXIS_READ(aux)); 151 for (i = 0; i < 16; i++) 152 printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i])); 153 for (i = 0; i < 16; i++) 154 printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i])); 155 printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]), 156 QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2])); 157 printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]), 158 QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2])); 159 printf("aux = %02x\n", QIXIS_READ(aux)); 160 printf("watch = %02x\n", QIXIS_READ(watch)); 161 printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys)); 162 printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl)); 163 printf("present = %02x\n", QIXIS_READ(present)); 164 printf("present2 = %02x\n", QIXIS_READ(present2)); 165 printf("clk_spd = %02x\n", QIXIS_READ(clk_spd)); 166 printf("stat_dut = %02x\n", QIXIS_READ(stat_dut)); 167 printf("stat_sys = %02x\n", QIXIS_READ(stat_sys)); 168 printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm)); 169 } 170 171 static void __qixis_dump_switch(void) 172 { 173 puts("Reverse engineering switch is not implemented for this board\n"); 174 } 175 176 void qixis_dump_switch(void) 177 __attribute__((weak, alias("__qixis_dump_switch"))); 178 179 int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 180 { 181 int i; 182 183 if (argc <= 1) { 184 clear_altbank(); 185 qixis_reset(); 186 } else if (strcmp(argv[1], "altbank") == 0) { 187 set_altbank(); 188 qixis_bank_reset(); 189 } else if (strcmp(argv[1], "watchdog") == 0) { 190 static char *period[9] = {"2s", "4s", "8s", "16s", "32s", 191 "1min", "2min", "4min", "8min"}; 192 u8 rcfg = QIXIS_READ(rcfg_ctl); 193 194 if (argv[2] == NULL) { 195 printf("qixis watchdog <watchdog_period>\n"); 196 return 0; 197 } 198 for (i = 0; i < ARRAY_SIZE(period); i++) { 199 if (strcmp(argv[2], period[i]) == 0) { 200 /* disable watchdog */ 201 QIXIS_WRITE(rcfg_ctl, 202 rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE); 203 QIXIS_WRITE(watch, ((i<<2) - 1)); 204 QIXIS_WRITE(rcfg_ctl, rcfg); 205 return 0; 206 } 207 } 208 } else if (strcmp(argv[1], "dump") == 0) { 209 qixis_dump_regs(); 210 return 0; 211 } else if (strcmp(argv[1], "switch") == 0) { 212 qixis_dump_switch(); 213 return 0; 214 } else { 215 printf("Invalid option: %s\n", argv[1]); 216 return 1; 217 } 218 219 return 0; 220 } 221 222 U_BOOT_CMD( 223 qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd, 224 "Reset the board using the FPGA sequencer", 225 "- hard reset to default bank\n" 226 "qixis_reset altbank - reset to alternate bank\n" 227 "qixis watchdog <watchdog_period> - set the watchdog period\n" 228 " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" 229 "qixis_reset dump - display the QIXIS registers\n" 230 "qixis_reset switch - display switch\n" 231 ); 232