1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
23d98b858SHaiying Wang /*
32feb4af0STimur Tabi * Copyright 2006,2010 Freescale Semiconductor
43d98b858SHaiying Wang * Jeff Brown
53d98b858SHaiying Wang * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
63d98b858SHaiying Wang */
73d98b858SHaiying Wang
83d98b858SHaiying Wang #include <common.h>
93d98b858SHaiying Wang #include <command.h>
105a8a163aSAndy Fleming #include <asm/io.h>
11ad8f8687SJon Loeliger
122feb4af0STimur Tabi #define pixis_base (u8 *)PIXIS_BASE
133d98b858SHaiying Wang
143d98b858SHaiying Wang /*
153d98b858SHaiying Wang * Simple board reset.
163d98b858SHaiying Wang */
pixis_reset(void)173d98b858SHaiying Wang void pixis_reset(void)
183d98b858SHaiying Wang {
19048e7efeSKumar Gala out_8(pixis_base + PIXIS_RST, 0);
203d98b858SHaiying Wang
212feb4af0STimur Tabi while (1);
222feb4af0STimur Tabi }
233d98b858SHaiying Wang
243d98b858SHaiying Wang /*
253d98b858SHaiying Wang * Per table 27, page 58 of MPC8641HPCN spec.
263d98b858SHaiying Wang */
set_px_sysclk(unsigned long sysclk)272feb4af0STimur Tabi static int set_px_sysclk(unsigned long sysclk)
283d98b858SHaiying Wang {
293d98b858SHaiying Wang u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
303d98b858SHaiying Wang
313d98b858SHaiying Wang switch (sysclk) {
323d98b858SHaiying Wang case 33:
333d98b858SHaiying Wang sysclk_s = 0x04;
343d98b858SHaiying Wang sysclk_r = 0x04;
353d98b858SHaiying Wang sysclk_v = 0x07;
363d98b858SHaiying Wang sysclk_aux = 0x00;
373d98b858SHaiying Wang break;
383d98b858SHaiying Wang case 40:
393d98b858SHaiying Wang sysclk_s = 0x01;
403d98b858SHaiying Wang sysclk_r = 0x1F;
413d98b858SHaiying Wang sysclk_v = 0x20;
423d98b858SHaiying Wang sysclk_aux = 0x01;
433d98b858SHaiying Wang break;
443d98b858SHaiying Wang case 50:
453d98b858SHaiying Wang sysclk_s = 0x01;
463d98b858SHaiying Wang sysclk_r = 0x1F;
473d98b858SHaiying Wang sysclk_v = 0x2A;
483d98b858SHaiying Wang sysclk_aux = 0x02;
493d98b858SHaiying Wang break;
503d98b858SHaiying Wang case 66:
513d98b858SHaiying Wang sysclk_s = 0x01;
523d98b858SHaiying Wang sysclk_r = 0x04;
533d98b858SHaiying Wang sysclk_v = 0x04;
543d98b858SHaiying Wang sysclk_aux = 0x03;
553d98b858SHaiying Wang break;
563d98b858SHaiying Wang case 83:
573d98b858SHaiying Wang sysclk_s = 0x01;
583d98b858SHaiying Wang sysclk_r = 0x1F;
593d98b858SHaiying Wang sysclk_v = 0x4B;
603d98b858SHaiying Wang sysclk_aux = 0x04;
613d98b858SHaiying Wang break;
623d98b858SHaiying Wang case 100:
633d98b858SHaiying Wang sysclk_s = 0x01;
643d98b858SHaiying Wang sysclk_r = 0x1F;
653d98b858SHaiying Wang sysclk_v = 0x5C;
663d98b858SHaiying Wang sysclk_aux = 0x05;
673d98b858SHaiying Wang break;
683d98b858SHaiying Wang case 134:
693d98b858SHaiying Wang sysclk_s = 0x06;
703d98b858SHaiying Wang sysclk_r = 0x1F;
713d98b858SHaiying Wang sysclk_v = 0x3B;
723d98b858SHaiying Wang sysclk_aux = 0x06;
733d98b858SHaiying Wang break;
743d98b858SHaiying Wang case 166:
753d98b858SHaiying Wang sysclk_s = 0x06;
763d98b858SHaiying Wang sysclk_r = 0x1F;
773d98b858SHaiying Wang sysclk_v = 0x4B;
783d98b858SHaiying Wang sysclk_aux = 0x07;
793d98b858SHaiying Wang break;
803d98b858SHaiying Wang default:
813d98b858SHaiying Wang printf("Unsupported SYSCLK frequency.\n");
823d98b858SHaiying Wang return 0;
833d98b858SHaiying Wang }
843d98b858SHaiying Wang
853d98b858SHaiying Wang vclkh = (sysclk_s << 5) | sysclk_r;
863d98b858SHaiying Wang vclkl = sysclk_v;
873d98b858SHaiying Wang
88048e7efeSKumar Gala out_8(pixis_base + PIXIS_VCLKH, vclkh);
89048e7efeSKumar Gala out_8(pixis_base + PIXIS_VCLKL, vclkl);
903d98b858SHaiying Wang
91048e7efeSKumar Gala out_8(pixis_base + PIXIS_AUX, sysclk_aux);
923d98b858SHaiying Wang
933d98b858SHaiying Wang return 1;
943d98b858SHaiying Wang }
953d98b858SHaiying Wang
962feb4af0STimur Tabi /* Set the CFG_SYSPLL bits
972feb4af0STimur Tabi *
982feb4af0STimur Tabi * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
992feb4af0STimur Tabi * read_from_px_regs() is called.
1002feb4af0STimur Tabi */
set_px_mpxpll(unsigned long mpxpll)1012feb4af0STimur Tabi static int set_px_mpxpll(unsigned long mpxpll)
1023d98b858SHaiying Wang {
1033d98b858SHaiying Wang switch (mpxpll) {
1043d98b858SHaiying Wang case 2:
1053d98b858SHaiying Wang case 4:
1063d98b858SHaiying Wang case 6:
1073d98b858SHaiying Wang case 8:
1083d98b858SHaiying Wang case 10:
1093d98b858SHaiying Wang case 12:
1103d98b858SHaiying Wang case 14:
1113d98b858SHaiying Wang case 16:
1122feb4af0STimur Tabi clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
1132feb4af0STimur Tabi return 1;
1142feb4af0STimur Tabi }
1152feb4af0STimur Tabi
1163d98b858SHaiying Wang printf("Unsupported MPXPLL ratio.\n");
1173d98b858SHaiying Wang return 0;
1183d98b858SHaiying Wang }
1193d98b858SHaiying Wang
set_px_corepll(unsigned long corepll)1202feb4af0STimur Tabi static int set_px_corepll(unsigned long corepll)
1213d98b858SHaiying Wang {
1223d98b858SHaiying Wang u8 val;
1233d98b858SHaiying Wang
1242feb4af0STimur Tabi switch (corepll) {
1253d98b858SHaiying Wang case 20:
1263d98b858SHaiying Wang val = 0x08;
1273d98b858SHaiying Wang break;
1283d98b858SHaiying Wang case 25:
1293d98b858SHaiying Wang val = 0x0C;
1303d98b858SHaiying Wang break;
1313d98b858SHaiying Wang case 30:
1323d98b858SHaiying Wang val = 0x10;
1333d98b858SHaiying Wang break;
1343d98b858SHaiying Wang case 35:
1353d98b858SHaiying Wang val = 0x1C;
1363d98b858SHaiying Wang break;
1373d98b858SHaiying Wang case 40:
1383d98b858SHaiying Wang val = 0x14;
1393d98b858SHaiying Wang break;
1403d98b858SHaiying Wang case 45:
1413d98b858SHaiying Wang val = 0x0E;
1423d98b858SHaiying Wang break;
1433d98b858SHaiying Wang default:
1443d98b858SHaiying Wang printf("Unsupported COREPLL ratio.\n");
1453d98b858SHaiying Wang return 0;
1463d98b858SHaiying Wang }
1473d98b858SHaiying Wang
1482feb4af0STimur Tabi clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
1493d98b858SHaiying Wang return 1;
1503d98b858SHaiying Wang }
1513d98b858SHaiying Wang
1522feb4af0STimur Tabi #ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
1532feb4af0STimur Tabi #define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
1542feb4af0STimur Tabi #endif
1553d98b858SHaiying Wang
1562feb4af0STimur Tabi /* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
1572feb4af0STimur Tabi *
1582feb4af0STimur Tabi * The PIXIS can be programmed to look at either the on-board dip switches
1592feb4af0STimur Tabi * or various other PIXIS registers to determine the values for COREPLL,
1602feb4af0STimur Tabi * MPXPLL, and SYSCLK.
1612feb4af0STimur Tabi *
1622feb4af0STimur Tabi * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
1632feb4af0STimur Tabi * register that tells the pixis to use the various PIXIS register.
1642feb4af0STimur Tabi */
read_from_px_regs(int set)1652feb4af0STimur Tabi static void read_from_px_regs(int set)
1663d98b858SHaiying Wang {
167048e7efeSKumar Gala u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
1683d98b858SHaiying Wang
1693d98b858SHaiying Wang if (set)
1702feb4af0STimur Tabi tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
1713d98b858SHaiying Wang else
1722feb4af0STimur Tabi tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
1732feb4af0STimur Tabi
174048e7efeSKumar Gala out_8(pixis_base + PIXIS_VCFGEN0, tmp);
1753d98b858SHaiying Wang }
1763d98b858SHaiying Wang
1772feb4af0STimur Tabi /* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
1782feb4af0STimur Tabi * register that tells the pixis to use the PX_VBOOT[LBMAP] register.
1792feb4af0STimur Tabi */
1802feb4af0STimur Tabi #ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
1812feb4af0STimur Tabi #define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
1822feb4af0STimur Tabi #endif
1833d98b858SHaiying Wang
1842feb4af0STimur Tabi /* Configure the source of the boot location
1852feb4af0STimur Tabi *
1862feb4af0STimur Tabi * The PIXIS can be programmed to look at either the on-board dip switches
1872feb4af0STimur Tabi * or the PX_VBOOT[LBMAP] register to determine where we should boot.
1882feb4af0STimur Tabi *
1892feb4af0STimur Tabi * If we want to boot from the alternate boot bank, we need to tell the PIXIS
1902feb4af0STimur Tabi * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
1912feb4af0STimur Tabi */
read_from_px_regs_altbank(int set)1922feb4af0STimur Tabi static void read_from_px_regs_altbank(int set)
1933d98b858SHaiying Wang {
194048e7efeSKumar Gala u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
1953d98b858SHaiying Wang
1963d98b858SHaiying Wang if (set)
1972feb4af0STimur Tabi tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
1983d98b858SHaiying Wang else
1992feb4af0STimur Tabi tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
2002feb4af0STimur Tabi
201048e7efeSKumar Gala out_8(pixis_base + PIXIS_VCFGEN1, tmp);
2023d98b858SHaiying Wang }
2033d98b858SHaiying Wang
2042feb4af0STimur Tabi /* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
2052feb4af0STimur Tabi * tells the PIXIS what the alternate flash bank is.
2062feb4af0STimur Tabi *
2072feb4af0STimur Tabi * Note that it's not really a mask. It contains the actual LBMAP bits that
2082feb4af0STimur Tabi * must be set to select the alternate bank. This code assumes that the
2092feb4af0STimur Tabi * primary bank has these bits set to 0, and the alternate bank has these
2102feb4af0STimur Tabi * bits set to 1.
2112feb4af0STimur Tabi */
2126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
2136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
214db74b3c1SJason Jin #endif
2153d98b858SHaiying Wang
2162feb4af0STimur Tabi /* Tell the PIXIS to boot from the default flash bank
2172feb4af0STimur Tabi *
2182feb4af0STimur Tabi * Program the default flash bank into the VBOOT register. This register is
2192feb4af0STimur Tabi * used only if PX_VCFGEN1[FLASH]=1.
2202feb4af0STimur Tabi */
clear_altbank(void)2212feb4af0STimur Tabi static void clear_altbank(void)
22216c3cde0SJames Yang {
2232feb4af0STimur Tabi clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
22416c3cde0SJames Yang }
22516c3cde0SJames Yang
2262feb4af0STimur Tabi /* Tell the PIXIS to boot from the alternate flash bank
2272feb4af0STimur Tabi *
2282feb4af0STimur Tabi * Program the alternate flash bank into the VBOOT register. This register is
2292feb4af0STimur Tabi * used only if PX_VCFGEN1[FLASH]=1.
2302feb4af0STimur Tabi */
set_altbank(void)2312feb4af0STimur Tabi static void set_altbank(void)
2323d98b858SHaiying Wang {
2332feb4af0STimur Tabi setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
2343d98b858SHaiying Wang }
2353d98b858SHaiying Wang
2362feb4af0STimur Tabi /* Reset the board with watchdog disabled.
2372feb4af0STimur Tabi *
2382feb4af0STimur Tabi * This respects the altbank setting.
2392feb4af0STimur Tabi */
set_px_go(void)2402feb4af0STimur Tabi static void set_px_go(void)
2413d98b858SHaiying Wang {
2422feb4af0STimur Tabi /* Disable the VELA sequencer and watchdog */
2432feb4af0STimur Tabi clrbits_8(pixis_base + PIXIS_VCTL, 9);
2443d98b858SHaiying Wang
2452feb4af0STimur Tabi /* Reboot by starting the VELA sequencer */
2462feb4af0STimur Tabi setbits_8(pixis_base + PIXIS_VCTL, 0x1);
2473d98b858SHaiying Wang
2482feb4af0STimur Tabi while (1);
2493d98b858SHaiying Wang }
2503d98b858SHaiying Wang
2512feb4af0STimur Tabi /* Reset the board with watchdog enabled.
2522feb4af0STimur Tabi *
2532feb4af0STimur Tabi * This respects the altbank setting.
2542feb4af0STimur Tabi */
set_px_go_with_watchdog(void)2552feb4af0STimur Tabi static void set_px_go_with_watchdog(void)
2563d98b858SHaiying Wang {
2572feb4af0STimur Tabi /* Disable the VELA sequencer */
2582feb4af0STimur Tabi clrbits_8(pixis_base + PIXIS_VCTL, 1);
2593d98b858SHaiying Wang
2602feb4af0STimur Tabi /* Enable the watchdog and reboot by starting the VELA sequencer */
2612feb4af0STimur Tabi setbits_8(pixis_base + PIXIS_VCTL, 0x9);
2623d98b858SHaiying Wang
2632feb4af0STimur Tabi while (1);
2643d98b858SHaiying Wang }
2653d98b858SHaiying Wang
2662feb4af0STimur Tabi /* Disable the watchdog
2672feb4af0STimur Tabi *
2682feb4af0STimur Tabi */
pixis_disable_watchdog_cmd(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])2692feb4af0STimur Tabi static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
27054841ab5SWolfgang Denk char * const argv[])
2713d98b858SHaiying Wang {
2722feb4af0STimur Tabi /* Disable the VELA sequencer and the watchdog */
2732feb4af0STimur Tabi clrbits_8(pixis_base + PIXIS_VCTL, 9);
2743d98b858SHaiying Wang
2753d98b858SHaiying Wang return 0;
2763d98b858SHaiying Wang }
2773d98b858SHaiying Wang
2783d98b858SHaiying Wang U_BOOT_CMD(
2793d98b858SHaiying Wang diswd, 1, 0, pixis_disable_watchdog_cmd,
2802fb2604dSPeter Tyser "Disable watchdog timer",
281a89c33dbSWolfgang Denk ""
282a89c33dbSWolfgang Denk );
2833d98b858SHaiying Wang
284bff188baSLiu Yu #ifdef CONFIG_PIXIS_SGMII_CMD
2852feb4af0STimur Tabi
2862feb4af0STimur Tabi /* Enable or disable SGMII mode for a TSEC
2872feb4af0STimur Tabi */
pixis_set_sgmii(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])28854841ab5SWolfgang Denk static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
2895a8a163aSAndy Fleming {
2905a8a163aSAndy Fleming int which_tsec = -1;
2912feb4af0STimur Tabi unsigned char mask;
2922feb4af0STimur Tabi unsigned char switch_mask;
2935a8a163aSAndy Fleming
2942feb4af0STimur Tabi if ((argc > 2) && (strcmp(argv[1], "all") != 0))
2955a8a163aSAndy Fleming which_tsec = simple_strtoul(argv[1], NULL, 0);
2965a8a163aSAndy Fleming
2975a8a163aSAndy Fleming switch (which_tsec) {
298bff188baSLiu Yu #ifdef CONFIG_TSEC1
2995a8a163aSAndy Fleming case 1:
3005a8a163aSAndy Fleming mask = PIXIS_VSPEED2_TSEC1SER;
3015a8a163aSAndy Fleming switch_mask = PIXIS_VCFGEN1_TSEC1SER;
3025a8a163aSAndy Fleming break;
303bff188baSLiu Yu #endif
304bff188baSLiu Yu #ifdef CONFIG_TSEC2
305bff188baSLiu Yu case 2:
306bff188baSLiu Yu mask = PIXIS_VSPEED2_TSEC2SER;
307bff188baSLiu Yu switch_mask = PIXIS_VCFGEN1_TSEC2SER;
308bff188baSLiu Yu break;
309bff188baSLiu Yu #endif
310bff188baSLiu Yu #ifdef CONFIG_TSEC3
3115a8a163aSAndy Fleming case 3:
3125a8a163aSAndy Fleming mask = PIXIS_VSPEED2_TSEC3SER;
3135a8a163aSAndy Fleming switch_mask = PIXIS_VCFGEN1_TSEC3SER;
3145a8a163aSAndy Fleming break;
315bff188baSLiu Yu #endif
316bff188baSLiu Yu #ifdef CONFIG_TSEC4
317bff188baSLiu Yu case 4:
318bff188baSLiu Yu mask = PIXIS_VSPEED2_TSEC4SER;
319bff188baSLiu Yu switch_mask = PIXIS_VCFGEN1_TSEC4SER;
320bff188baSLiu Yu break;
321bff188baSLiu Yu #endif
3225a8a163aSAndy Fleming default:
323bff188baSLiu Yu mask = PIXIS_VSPEED2_MASK;
324bff188baSLiu Yu switch_mask = PIXIS_VCFGEN1_MASK;
3255a8a163aSAndy Fleming break;
3265a8a163aSAndy Fleming }
3275a8a163aSAndy Fleming
3285a8a163aSAndy Fleming /* Toggle whether the switches or FPGA control the settings */
3295a8a163aSAndy Fleming if (!strcmp(argv[argc - 1], "switch"))
330048e7efeSKumar Gala clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
3315a8a163aSAndy Fleming else
332048e7efeSKumar Gala setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
3335a8a163aSAndy Fleming
3345a8a163aSAndy Fleming /* If it's not the switches, enable or disable SGMII, as specified */
3355a8a163aSAndy Fleming if (!strcmp(argv[argc - 1], "on"))
336048e7efeSKumar Gala clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
3375a8a163aSAndy Fleming else if (!strcmp(argv[argc - 1], "off"))
338048e7efeSKumar Gala setbits_8(pixis_base + PIXIS_VSPEED2, mask);
3395a8a163aSAndy Fleming
3405a8a163aSAndy Fleming return 0;
3415a8a163aSAndy Fleming }
3425a8a163aSAndy Fleming
3435a8a163aSAndy Fleming U_BOOT_CMD(
3446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
3455a8a163aSAndy Fleming "pixis_set_sgmii"
3465a8a163aSAndy Fleming " - Enable or disable SGMII mode for a given TSEC \n",
3475a8a163aSAndy Fleming "\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
3485a8a163aSAndy Fleming " TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
3495a8a163aSAndy Fleming " on - enables SGMII\n"
3505a8a163aSAndy Fleming " off - disables SGMII\n"
351a89c33dbSWolfgang Denk " switch - use switch settings"
352a89c33dbSWolfgang Denk );
3532feb4af0STimur Tabi
3545a8a163aSAndy Fleming #endif
3555a8a163aSAndy Fleming
3563d98b858SHaiying Wang /*
3573d98b858SHaiying Wang * This function takes the non-integral cpu:mpx pll ratio
3583d98b858SHaiying Wang * and converts it to an integer that can be used to assign
3593d98b858SHaiying Wang * FPGA register values.
3603d98b858SHaiying Wang * input: strptr i.e. argv[2]
3613d98b858SHaiying Wang */
strfractoint(char * strptr)3622feb4af0STimur Tabi static unsigned long strfractoint(char *strptr)
3633d98b858SHaiying Wang {
3642feb4af0STimur Tabi int i, j;
3653d98b858SHaiying Wang int mulconst;
3668dbd4b74SKumar Gala int no_dec = 0;
3672feb4af0STimur Tabi unsigned long intval = 0, decval = 0;
3682feb4af0STimur Tabi char intarr[3], decarr[3];
3693d98b858SHaiying Wang
3703d98b858SHaiying Wang /* Assign the integer part to intarr[]
3713d98b858SHaiying Wang * If there is no decimal point i.e.
3723d98b858SHaiying Wang * if the ratio is an integral value
3733d98b858SHaiying Wang * simply create the intarr.
3743d98b858SHaiying Wang */
3753d98b858SHaiying Wang i = 0;
37616c3cde0SJames Yang while (strptr[i] != '.') {
3773d98b858SHaiying Wang if (strptr[i] == 0) {
3783d98b858SHaiying Wang no_dec = 1;
3793d98b858SHaiying Wang break;
3803d98b858SHaiying Wang }
3813d98b858SHaiying Wang intarr[i] = strptr[i];
3823d98b858SHaiying Wang i++;
3833d98b858SHaiying Wang }
3843d98b858SHaiying Wang
3853d98b858SHaiying Wang intarr[i] = '\0';
3863d98b858SHaiying Wang
3873d98b858SHaiying Wang if (no_dec) {
3883d98b858SHaiying Wang /* Currently needed only for single digit corepll ratios */
3893d98b858SHaiying Wang mulconst = 10;
3903d98b858SHaiying Wang decval = 0;
3913d98b858SHaiying Wang } else {
3923d98b858SHaiying Wang j = 0;
3933d98b858SHaiying Wang i++; /* Skipping the decimal point */
39416c3cde0SJames Yang while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
3953d98b858SHaiying Wang decarr[j] = strptr[i];
3963d98b858SHaiying Wang i++;
3973d98b858SHaiying Wang j++;
3983d98b858SHaiying Wang }
3993d98b858SHaiying Wang
4003d98b858SHaiying Wang decarr[j] = '\0';
4013d98b858SHaiying Wang
4023d98b858SHaiying Wang mulconst = 1;
4032feb4af0STimur Tabi for (i = 0; i < j; i++)
4043d98b858SHaiying Wang mulconst *= 10;
4052feb4af0STimur Tabi decval = simple_strtoul(decarr, NULL, 10);
4063d98b858SHaiying Wang }
4073d98b858SHaiying Wang
4082feb4af0STimur Tabi intval = simple_strtoul(intarr, NULL, 10);
4093d98b858SHaiying Wang intval = intval * mulconst;
4103d98b858SHaiying Wang
4112feb4af0STimur Tabi return intval + decval;
4123d98b858SHaiying Wang }
4133d98b858SHaiying Wang
pixis_reset_cmd(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])41454841ab5SWolfgang Denk static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
4153d98b858SHaiying Wang {
41616c3cde0SJames Yang unsigned int i;
41716c3cde0SJames Yang char *p_cf = NULL;
41816c3cde0SJames Yang char *p_cf_sysclk = NULL;
41916c3cde0SJames Yang char *p_cf_corepll = NULL;
42016c3cde0SJames Yang char *p_cf_mpxpll = NULL;
42116c3cde0SJames Yang char *p_altbank = NULL;
42216c3cde0SJames Yang char *p_wd = NULL;
4232feb4af0STimur Tabi int unknown_param = 0;
4243d98b858SHaiying Wang
4253d98b858SHaiying Wang /*
4263d98b858SHaiying Wang * No args is a simple reset request.
4273d98b858SHaiying Wang */
4283d98b858SHaiying Wang if (argc <= 1) {
4293d98b858SHaiying Wang pixis_reset();
4303d98b858SHaiying Wang /* not reached */
4313d98b858SHaiying Wang }
4323d98b858SHaiying Wang
43316c3cde0SJames Yang for (i = 1; i < argc; i++) {
43416c3cde0SJames Yang if (strcmp(argv[i], "cf") == 0) {
43516c3cde0SJames Yang p_cf = argv[i];
43616c3cde0SJames Yang if (i + 3 >= argc) {
43716c3cde0SJames Yang break;
43816c3cde0SJames Yang }
43916c3cde0SJames Yang p_cf_sysclk = argv[i+1];
44016c3cde0SJames Yang p_cf_corepll = argv[i+2];
44116c3cde0SJames Yang p_cf_mpxpll = argv[i+3];
44216c3cde0SJames Yang i += 3;
44316c3cde0SJames Yang continue;
44416c3cde0SJames Yang }
44516c3cde0SJames Yang
44616c3cde0SJames Yang if (strcmp(argv[i], "altbank") == 0) {
44716c3cde0SJames Yang p_altbank = argv[i];
44816c3cde0SJames Yang continue;
44916c3cde0SJames Yang }
45016c3cde0SJames Yang
45116c3cde0SJames Yang if (strcmp(argv[i], "wd") == 0) {
45216c3cde0SJames Yang p_wd = argv[i];
45316c3cde0SJames Yang continue;
45416c3cde0SJames Yang }
45516c3cde0SJames Yang
45616c3cde0SJames Yang unknown_param = 1;
45716c3cde0SJames Yang }
4583d98b858SHaiying Wang
4593d98b858SHaiying Wang /*
46016c3cde0SJames Yang * Check that cf has all required parms
4613d98b858SHaiying Wang */
46216c3cde0SJames Yang if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
46316c3cde0SJames Yang || unknown_param) {
464f7fecc3eSEd Swarthout #ifdef CONFIG_SYS_LONGHELP
46516c3cde0SJames Yang puts(cmdtp->help);
4665bdeff32SYork Sun putc('\n');
467f7fecc3eSEd Swarthout #endif
4683d98b858SHaiying Wang return 1;
4693d98b858SHaiying Wang }
4703d98b858SHaiying Wang
4713d98b858SHaiying Wang /*
47216c3cde0SJames Yang * PIXIS seems to be sensitive to the ordering of
47316c3cde0SJames Yang * the registers that are touched.
4743d98b858SHaiying Wang */
4753d98b858SHaiying Wang read_from_px_regs(0);
47616c3cde0SJames Yang
4772feb4af0STimur Tabi if (p_altbank)
4783d98b858SHaiying Wang read_from_px_regs_altbank(0);
4792feb4af0STimur Tabi
48016c3cde0SJames Yang clear_altbank();
48116c3cde0SJames Yang
48216c3cde0SJames Yang /*
48316c3cde0SJames Yang * Clock configuration specified.
48416c3cde0SJames Yang */
48516c3cde0SJames Yang if (p_cf) {
48616c3cde0SJames Yang unsigned long sysclk;
48716c3cde0SJames Yang unsigned long corepll;
48816c3cde0SJames Yang unsigned long mpxpll;
48916c3cde0SJames Yang
49016c3cde0SJames Yang sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
4912feb4af0STimur Tabi corepll = strfractoint(p_cf_corepll);
49216c3cde0SJames Yang mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
49316c3cde0SJames Yang
49416c3cde0SJames Yang if (!(set_px_sysclk(sysclk)
49516c3cde0SJames Yang && set_px_corepll(corepll)
49616c3cde0SJames Yang && set_px_mpxpll(mpxpll))) {
497f7fecc3eSEd Swarthout #ifdef CONFIG_SYS_LONGHELP
49816c3cde0SJames Yang puts(cmdtp->help);
4995bdeff32SYork Sun putc('\n');
500f7fecc3eSEd Swarthout #endif
5013d98b858SHaiying Wang return 1;
5023d98b858SHaiying Wang }
50316c3cde0SJames Yang read_from_px_regs(1);
50416c3cde0SJames Yang }
50516c3cde0SJames Yang
50616c3cde0SJames Yang /*
50716c3cde0SJames Yang * Altbank specified
50816c3cde0SJames Yang *
50916c3cde0SJames Yang * NOTE CHANGE IN BEHAVIOR: previous code would default
51016c3cde0SJames Yang * to enabling watchdog if altbank is specified.
51116c3cde0SJames Yang * Now the watchdog must be enabled explicitly using 'wd'.
51216c3cde0SJames Yang */
51316c3cde0SJames Yang if (p_altbank) {
5143d98b858SHaiying Wang set_altbank();
5153d98b858SHaiying Wang read_from_px_regs_altbank(1);
51616c3cde0SJames Yang }
5173d98b858SHaiying Wang
5183d98b858SHaiying Wang /*
51916c3cde0SJames Yang * Reset with watchdog specified.
5203d98b858SHaiying Wang */
5212feb4af0STimur Tabi if (p_wd)
5223d98b858SHaiying Wang set_px_go_with_watchdog();
5232feb4af0STimur Tabi else
52416c3cde0SJames Yang set_px_go();
5253d98b858SHaiying Wang
5263d98b858SHaiying Wang /*
52716c3cde0SJames Yang * Shouldn't be reached.
5283d98b858SHaiying Wang */
5293d98b858SHaiying Wang return 0;
5303d98b858SHaiying Wang }
5313d98b858SHaiying Wang
5323d98b858SHaiying Wang
5333d98b858SHaiying Wang U_BOOT_CMD(
5346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
5352fb2604dSPeter Tyser "Reset the board using the FPGA sequencer",
5363d98b858SHaiying Wang " pixis_reset\n"
5373d98b858SHaiying Wang " pixis_reset [altbank]\n"
5383d98b858SHaiying Wang " pixis_reset altbank wd\n"
5393d98b858SHaiying Wang " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
540a89c33dbSWolfgang Denk " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
5413d98b858SHaiying Wang );
542