xref: /openbmc/u-boot/board/freescale/common/pfuze.c (revision 7c4213f6)
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <errno.h>
9 #include <power/pmic.h>
10 #include <power/pfuze100_pmic.h>
11 
12 #ifndef CONFIG_DM_PMIC_PFUZE100
13 int pfuze_mode_init(struct pmic *p, u32 mode)
14 {
15 	unsigned char offset, i, switch_num;
16 	u32 id;
17 	int ret;
18 
19 	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
20 	id = id & 0xf;
21 
22 	if (id == 0) {
23 		switch_num = 6;
24 		offset = PFUZE100_SW1CMODE;
25 	} else if (id == 1) {
26 		switch_num = 4;
27 		offset = PFUZE100_SW2MODE;
28 	} else {
29 		printf("Not supported, id=%d\n", id);
30 		return -EINVAL;
31 	}
32 
33 	ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
34 	if (ret < 0) {
35 		printf("Set SW1AB mode error!\n");
36 		return ret;
37 	}
38 
39 	for (i = 0; i < switch_num - 1; i++) {
40 		ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
41 		if (ret < 0) {
42 			printf("Set switch 0x%x mode error!\n",
43 			       offset + i * SWITCH_SIZE);
44 			return ret;
45 		}
46 	}
47 
48 	return ret;
49 }
50 
51 struct pmic *pfuze_common_init(unsigned char i2cbus)
52 {
53 	struct pmic *p;
54 	int ret;
55 	unsigned int reg;
56 
57 	ret = power_pfuze100_init(i2cbus);
58 	if (ret)
59 		return NULL;
60 
61 	p = pmic_get("PFUZE100");
62 	ret = pmic_probe(p);
63 	if (ret)
64 		return NULL;
65 
66 	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
67 	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
68 
69 	/* Set SW1AB stanby volage to 0.975V */
70 	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
71 	reg &= ~SW1x_STBY_MASK;
72 	reg |= SW1x_0_975V;
73 	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
74 
75 	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
76 	pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
77 	reg &= ~SW1xCONF_DVSSPEED_MASK;
78 	reg |= SW1xCONF_DVSSPEED_4US;
79 	pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
80 
81 	/* Set SW1C standby voltage to 0.975V */
82 	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
83 	reg &= ~SW1x_STBY_MASK;
84 	reg |= SW1x_0_975V;
85 	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
86 
87 	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
88 	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
89 	reg &= ~SW1xCONF_DVSSPEED_MASK;
90 	reg |= SW1xCONF_DVSSPEED_4US;
91 	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
92 
93 	return p;
94 }
95 #endif
96