1 /* 2 * Copyright 2008-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/mmu.h> 12 13 struct fsl_e_tlb_entry tlb_table[] = { 14 /* TLB 0 - for temp stack in cache */ 15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 16 CONFIG_SYS_INIT_RAM_ADDR_PHYS, 17 MAS3_SW|MAS3_SR, 0, 18 0, 0, BOOKE_PAGESZ_4K, 0), 19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 20 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 21 MAS3_SW|MAS3_SR, 0, 22 0, 0, BOOKE_PAGESZ_4K, 0), 23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 24 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 25 MAS3_SW|MAS3_SR, 0, 26 0, 0, BOOKE_PAGESZ_4K, 0), 27 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 28 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 29 MAS3_SW|MAS3_SR, 0, 30 0, 0, BOOKE_PAGESZ_4K, 0), 31 #ifdef CPLD_BASE 32 SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS, 33 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 34 0, 0, BOOKE_PAGESZ_4K, 0), 35 #endif 36 37 #ifdef PIXIS_BASE 38 SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, 39 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 40 0, 0, BOOKE_PAGESZ_4K, 0), 41 #endif 42 43 /* TLB 1 */ 44 /* *I*** - Covers boot page */ 45 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 46 47 #if !defined(CONFIG_SECURE_BOOT) 48 /* 49 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 50 * SRAM is at 0xfff00000, it covered the 0xfffff000. 51 */ 52 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 53 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 54 0, 0, BOOKE_PAGESZ_1M, 1), 55 #else 56 /* 57 * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot 58 * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR, 59 * and virtual address is CONFIG_SYS_MONITOR_BASE 60 */ 61 62 SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000, 63 CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, 64 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 65 0, 0, BOOKE_PAGESZ_1M, 1), 66 #endif 67 68 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 69 /* 70 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the 71 * space is at 0xfff00000, it covered the 0xfffff000. 72 */ 73 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, 74 CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, 75 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 76 0, 0, BOOKE_PAGESZ_1M, 1), 77 #else 78 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 79 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 80 0, 0, BOOKE_PAGESZ_4K, 1), 81 #endif 82 83 /* *I*G* - CCSRBAR */ 84 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 85 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 86 0, 1, BOOKE_PAGESZ_16M, 1), 87 88 /* *I*G* - Flash, localbus */ 89 /* This will be changed to *I*G* after relocation to RAM. */ 90 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 91 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 92 0, 2, BOOKE_PAGESZ_256M, 1), 93 94 /* *I*G* - PCI */ 95 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 96 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 97 0, 3, BOOKE_PAGESZ_1G, 1), 98 99 /* *I*G* - PCI */ 100 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 101 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 102 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 103 0, 4, BOOKE_PAGESZ_256M, 1), 104 105 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 106 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 107 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 108 0, 5, BOOKE_PAGESZ_256M, 1), 109 110 /* *I*G* - PCI I/O */ 111 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 112 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 113 0, 6, BOOKE_PAGESZ_256K, 1), 114 115 /* Bman/Qman */ 116 #ifdef CONFIG_SYS_BMAN_MEM_PHYS 117 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 118 MAS3_SW|MAS3_SR, 0, 119 0, 9, BOOKE_PAGESZ_1M, 1), 120 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, 121 CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, 122 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 123 0, 10, BOOKE_PAGESZ_1M, 1), 124 #endif 125 #ifdef CONFIG_SYS_QMAN_MEM_PHYS 126 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 127 MAS3_SW|MAS3_SR, 0, 128 0, 11, BOOKE_PAGESZ_1M, 1), 129 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, 130 CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, 131 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 132 0, 12, BOOKE_PAGESZ_1M, 1), 133 #endif 134 #ifdef CONFIG_SYS_DCSRBAR_PHYS 135 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 136 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 137 0, 13, BOOKE_PAGESZ_4M, 1), 138 #endif 139 #ifdef CONFIG_SYS_NAND_BASE 140 /* 141 * *I*G - NAND 142 * entry 14 and 15 has been used hard coded, they will be disabled 143 * in cpu_init_f, so we use entry 16 for nand. 144 */ 145 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 146 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 147 0, 16, BOOKE_PAGESZ_1M, 1), 148 #endif 149 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 150 /* 151 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for 152 * fetching ucode and ENV from master 153 */ 154 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, 155 CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, 156 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 157 0, 17, BOOKE_PAGESZ_1M, 1), 158 #endif 159 }; 160 161 int num_tlb_entries = ARRAY_SIZE(tlb_table); 162