1360275b3SKumar Gala /* 2360275b3SKumar Gala * Copyright 2008-2011 Freescale Semiconductor, Inc. 3360275b3SKumar Gala * 4360275b3SKumar Gala * (C) Copyright 2000 5360275b3SKumar Gala * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6360275b3SKumar Gala * 7360275b3SKumar Gala * See file CREDITS for list of people who contributed to this 8360275b3SKumar Gala * project. 9360275b3SKumar Gala * 10360275b3SKumar Gala * This program is free software; you can redistribute it and/or 11360275b3SKumar Gala * modify it under the terms of the GNU General Public License as 12360275b3SKumar Gala * published by the Free Software Foundation; either version 2 of 13360275b3SKumar Gala * the License, or (at your option) any later version. 14360275b3SKumar Gala * 15360275b3SKumar Gala * This program is distributed in the hope that it will be useful, 16360275b3SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 17360275b3SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18360275b3SKumar Gala * GNU General Public License for more details. 19360275b3SKumar Gala * 20360275b3SKumar Gala * You should have received a copy of the GNU General Public License 21360275b3SKumar Gala * along with this program; if not, write to the Free Software 22360275b3SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23360275b3SKumar Gala * MA 02111-1307 USA 24360275b3SKumar Gala */ 25360275b3SKumar Gala 26360275b3SKumar Gala #include <common.h> 27360275b3SKumar Gala #include <asm/mmu.h> 28360275b3SKumar Gala 29360275b3SKumar Gala struct fsl_e_tlb_entry tlb_table[] = { 30360275b3SKumar Gala /* TLB 0 - for temp stack in cache */ 31360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 32360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS, 33360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 34360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 35360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 36360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 37360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 38360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 39360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 40360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 41360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 42360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 43360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 44360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 45360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 46360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 47*f8bc7bb5SKumar Gala #ifdef CPLD_BASE 48*f8bc7bb5SKumar Gala SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS, 49*f8bc7bb5SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 50*f8bc7bb5SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 51*f8bc7bb5SKumar Gala #endif 52360275b3SKumar Gala 53*f8bc7bb5SKumar Gala #ifdef PIXIS_BASE 54360275b3SKumar Gala SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, 55360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 56360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 57*f8bc7bb5SKumar Gala #endif 58360275b3SKumar Gala 59360275b3SKumar Gala /* TLB 1 */ 60360275b3SKumar Gala /* *I*** - Covers boot page */ 61360275b3SKumar Gala #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 62360275b3SKumar Gala /* 63360275b3SKumar Gala * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 64360275b3SKumar Gala * SRAM is at 0xfff00000, it covered the 0xfffff000. 65360275b3SKumar Gala */ 66360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 67360275b3SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 68360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_1M, 1), 69360275b3SKumar Gala #else 70360275b3SKumar Gala SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 71360275b3SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 72360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 1), 73360275b3SKumar Gala #endif 74360275b3SKumar Gala 75360275b3SKumar Gala /* *I*G* - CCSRBAR */ 76360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 77360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 78360275b3SKumar Gala 0, 1, BOOKE_PAGESZ_16M, 1), 79360275b3SKumar Gala 80360275b3SKumar Gala /* *I*G* - Flash, localbus */ 81360275b3SKumar Gala /* This will be changed to *I*G* after relocation to RAM. */ 82360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 83360275b3SKumar Gala MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 84360275b3SKumar Gala 0, 2, BOOKE_PAGESZ_256M, 1), 85360275b3SKumar Gala 86360275b3SKumar Gala /* *I*G* - PCI */ 87360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 88360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 89360275b3SKumar Gala 0, 3, BOOKE_PAGESZ_1G, 1), 90360275b3SKumar Gala 91360275b3SKumar Gala /* *I*G* - PCI */ 92360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 93360275b3SKumar Gala CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 94360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 95360275b3SKumar Gala 0, 4, BOOKE_PAGESZ_256M, 1), 96360275b3SKumar Gala 97360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 98360275b3SKumar Gala CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 99360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 100360275b3SKumar Gala 0, 5, BOOKE_PAGESZ_256M, 1), 101360275b3SKumar Gala 102360275b3SKumar Gala /* *I*G* - PCI I/O */ 103360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 104360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 105360275b3SKumar Gala 0, 6, BOOKE_PAGESZ_256K, 1), 106360275b3SKumar Gala 107360275b3SKumar Gala /* Bman/Qman */ 108360275b3SKumar Gala #ifdef CONFIG_SYS_BMAN_MEM_PHYS 109360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 110360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 111360275b3SKumar Gala 0, 9, BOOKE_PAGESZ_1M, 1), 112360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, 113360275b3SKumar Gala CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, 114360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 115360275b3SKumar Gala 0, 10, BOOKE_PAGESZ_1M, 1), 116360275b3SKumar Gala #endif 117360275b3SKumar Gala #ifdef CONFIG_SYS_QMAN_MEM_PHYS 118360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 119360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 120360275b3SKumar Gala 0, 11, BOOKE_PAGESZ_1M, 1), 121360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, 122360275b3SKumar Gala CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, 123360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 124360275b3SKumar Gala 0, 12, BOOKE_PAGESZ_1M, 1), 125360275b3SKumar Gala #endif 126360275b3SKumar Gala #ifdef CONFIG_SYS_DCSRBAR_PHYS 127360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 128360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 129360275b3SKumar Gala 0, 13, BOOKE_PAGESZ_4M, 1), 130360275b3SKumar Gala #endif 131360275b3SKumar Gala #ifdef CONFIG_SYS_NAND_BASE 132360275b3SKumar Gala /* 133360275b3SKumar Gala * *I*G - NAND 134360275b3SKumar Gala * entry 14 and 15 has been used hard coded, they will be disabled 135360275b3SKumar Gala * in cpu_init_f, so we use entry 16 for nand. 136360275b3SKumar Gala */ 137360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 138360275b3SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 139360275b3SKumar Gala 0, 16, BOOKE_PAGESZ_1M, 1), 140360275b3SKumar Gala #endif 141360275b3SKumar Gala }; 142360275b3SKumar Gala 143360275b3SKumar Gala int num_tlb_entries = ARRAY_SIZE(tlb_table); 144