1360275b3SKumar Gala /* 2360275b3SKumar Gala * Copyright 2008-2011 Freescale Semiconductor, Inc. 3360275b3SKumar Gala * 4360275b3SKumar Gala * (C) Copyright 2000 5360275b3SKumar Gala * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6360275b3SKumar Gala * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8360275b3SKumar Gala */ 9360275b3SKumar Gala 10360275b3SKumar Gala #include <common.h> 11360275b3SKumar Gala #include <asm/mmu.h> 12360275b3SKumar Gala 13360275b3SKumar Gala struct fsl_e_tlb_entry tlb_table[] = { 14360275b3SKumar Gala /* TLB 0 - for temp stack in cache */ 15360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 16360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS, 17360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 18360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 19360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 20360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 21360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 22360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 23360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 24360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 25360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 26360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 27360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 28360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 29360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 30360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 31f8bc7bb5SKumar Gala #ifdef CPLD_BASE 32f8bc7bb5SKumar Gala SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS, 33f8bc7bb5SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 34f8bc7bb5SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 35f8bc7bb5SKumar Gala #endif 36360275b3SKumar Gala 37f8bc7bb5SKumar Gala #ifdef PIXIS_BASE 38360275b3SKumar Gala SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, 39360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 40360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 41f8bc7bb5SKumar Gala #endif 42360275b3SKumar Gala 43360275b3SKumar Gala /* TLB 1 */ 44360275b3SKumar Gala /* *I*** - Covers boot page */ 45360275b3SKumar Gala #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 46*467a40dfSAneesh Bansal 47*467a40dfSAneesh Bansal #if !defined(CONFIG_SECURE_BOOT) 48360275b3SKumar Gala /* 49360275b3SKumar Gala * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 50360275b3SKumar Gala * SRAM is at 0xfff00000, it covered the 0xfffff000. 51360275b3SKumar Gala */ 52360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 53360275b3SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 54360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_1M, 1), 55*467a40dfSAneesh Bansal #else 56*467a40dfSAneesh Bansal /* 57*467a40dfSAneesh Bansal * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot 58*467a40dfSAneesh Bansal * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR, 59*467a40dfSAneesh Bansal * and virtual address is CONFIG_SYS_MONITOR_BASE 60*467a40dfSAneesh Bansal */ 61*467a40dfSAneesh Bansal 62*467a40dfSAneesh Bansal SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000, 63*467a40dfSAneesh Bansal CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, 64*467a40dfSAneesh Bansal MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 65*467a40dfSAneesh Bansal 0, 0, BOOKE_PAGESZ_1M, 1), 66*467a40dfSAneesh Bansal #endif 67*467a40dfSAneesh Bansal 68461632bdSLiu Gang #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 69292dc6c5SLiu Gang /* 70461632bdSLiu Gang * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the 71292dc6c5SLiu Gang * space is at 0xfff00000, it covered the 0xfffff000. 72292dc6c5SLiu Gang */ 73461632bdSLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, 74461632bdSLiu Gang CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, 75292dc6c5SLiu Gang MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 76292dc6c5SLiu Gang 0, 0, BOOKE_PAGESZ_1M, 1), 77360275b3SKumar Gala #else 78360275b3SKumar Gala SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 79360275b3SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 80360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 1), 81360275b3SKumar Gala #endif 82360275b3SKumar Gala 83360275b3SKumar Gala /* *I*G* - CCSRBAR */ 84360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 85360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 86360275b3SKumar Gala 0, 1, BOOKE_PAGESZ_16M, 1), 87360275b3SKumar Gala 88360275b3SKumar Gala /* *I*G* - Flash, localbus */ 89360275b3SKumar Gala /* This will be changed to *I*G* after relocation to RAM. */ 90360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 91360275b3SKumar Gala MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 92360275b3SKumar Gala 0, 2, BOOKE_PAGESZ_256M, 1), 93360275b3SKumar Gala 94360275b3SKumar Gala /* *I*G* - PCI */ 95360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 96360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 97360275b3SKumar Gala 0, 3, BOOKE_PAGESZ_1G, 1), 98360275b3SKumar Gala 99360275b3SKumar Gala /* *I*G* - PCI */ 100360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 101360275b3SKumar Gala CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 102360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 103360275b3SKumar Gala 0, 4, BOOKE_PAGESZ_256M, 1), 104360275b3SKumar Gala 105360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 106360275b3SKumar Gala CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 107360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 108360275b3SKumar Gala 0, 5, BOOKE_PAGESZ_256M, 1), 109360275b3SKumar Gala 110360275b3SKumar Gala /* *I*G* - PCI I/O */ 111360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 112360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 113360275b3SKumar Gala 0, 6, BOOKE_PAGESZ_256K, 1), 114360275b3SKumar Gala 115360275b3SKumar Gala /* Bman/Qman */ 116360275b3SKumar Gala #ifdef CONFIG_SYS_BMAN_MEM_PHYS 117360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 118360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 119360275b3SKumar Gala 0, 9, BOOKE_PAGESZ_1M, 1), 120360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, 121360275b3SKumar Gala CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, 122360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 123360275b3SKumar Gala 0, 10, BOOKE_PAGESZ_1M, 1), 124360275b3SKumar Gala #endif 125360275b3SKumar Gala #ifdef CONFIG_SYS_QMAN_MEM_PHYS 126360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 127360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 128360275b3SKumar Gala 0, 11, BOOKE_PAGESZ_1M, 1), 129360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, 130360275b3SKumar Gala CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, 131360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 132360275b3SKumar Gala 0, 12, BOOKE_PAGESZ_1M, 1), 133360275b3SKumar Gala #endif 134360275b3SKumar Gala #ifdef CONFIG_SYS_DCSRBAR_PHYS 135360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 136360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 137360275b3SKumar Gala 0, 13, BOOKE_PAGESZ_4M, 1), 138360275b3SKumar Gala #endif 139360275b3SKumar Gala #ifdef CONFIG_SYS_NAND_BASE 140360275b3SKumar Gala /* 141360275b3SKumar Gala * *I*G - NAND 142360275b3SKumar Gala * entry 14 and 15 has been used hard coded, they will be disabled 143360275b3SKumar Gala * in cpu_init_f, so we use entry 16 for nand. 144360275b3SKumar Gala */ 145360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 146360275b3SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 147360275b3SKumar Gala 0, 16, BOOKE_PAGESZ_1M, 1), 148360275b3SKumar Gala #endif 149461632bdSLiu Gang #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 1503f1af81bSLiu Gang /* 151461632bdSLiu Gang * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for 152461632bdSLiu Gang * fetching ucode and ENV from master 1533f1af81bSLiu Gang */ 154461632bdSLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, 155461632bdSLiu Gang CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, 1563f1af81bSLiu Gang MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 1573f1af81bSLiu Gang 0, 17, BOOKE_PAGESZ_1M, 1), 1583f1af81bSLiu Gang #endif 159360275b3SKumar Gala }; 160360275b3SKumar Gala 161360275b3SKumar Gala int num_tlb_entries = ARRAY_SIZE(tlb_table); 162