1*360275b3SKumar Gala /* 2*360275b3SKumar Gala * Copyright 2008-2011 Freescale Semiconductor, Inc. 3*360275b3SKumar Gala * 4*360275b3SKumar Gala * (C) Copyright 2000 5*360275b3SKumar Gala * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*360275b3SKumar Gala * 7*360275b3SKumar Gala * See file CREDITS for list of people who contributed to this 8*360275b3SKumar Gala * project. 9*360275b3SKumar Gala * 10*360275b3SKumar Gala * This program is free software; you can redistribute it and/or 11*360275b3SKumar Gala * modify it under the terms of the GNU General Public License as 12*360275b3SKumar Gala * published by the Free Software Foundation; either version 2 of 13*360275b3SKumar Gala * the License, or (at your option) any later version. 14*360275b3SKumar Gala * 15*360275b3SKumar Gala * This program is distributed in the hope that it will be useful, 16*360275b3SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 17*360275b3SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18*360275b3SKumar Gala * GNU General Public License for more details. 19*360275b3SKumar Gala * 20*360275b3SKumar Gala * You should have received a copy of the GNU General Public License 21*360275b3SKumar Gala * along with this program; if not, write to the Free Software 22*360275b3SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23*360275b3SKumar Gala * MA 02111-1307 USA 24*360275b3SKumar Gala */ 25*360275b3SKumar Gala 26*360275b3SKumar Gala #include <common.h> 27*360275b3SKumar Gala #include <asm/mmu.h> 28*360275b3SKumar Gala 29*360275b3SKumar Gala struct fsl_e_tlb_entry tlb_table[] = { 30*360275b3SKumar Gala /* TLB 0 - for temp stack in cache */ 31*360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 32*360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS, 33*360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 34*360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 35*360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 36*360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 37*360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 38*360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 39*360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 40*360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 41*360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 42*360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 43*360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 44*360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 45*360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 46*360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 47*360275b3SKumar Gala 48*360275b3SKumar Gala SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, 49*360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 50*360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 51*360275b3SKumar Gala 52*360275b3SKumar Gala /* TLB 1 */ 53*360275b3SKumar Gala /* *I*** - Covers boot page */ 54*360275b3SKumar Gala #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 55*360275b3SKumar Gala /* 56*360275b3SKumar Gala * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 57*360275b3SKumar Gala * SRAM is at 0xfff00000, it covered the 0xfffff000. 58*360275b3SKumar Gala */ 59*360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 60*360275b3SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 61*360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_1M, 1), 62*360275b3SKumar Gala #else 63*360275b3SKumar Gala SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 64*360275b3SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 65*360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 1), 66*360275b3SKumar Gala #endif 67*360275b3SKumar Gala 68*360275b3SKumar Gala /* *I*G* - CCSRBAR */ 69*360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 70*360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 71*360275b3SKumar Gala 0, 1, BOOKE_PAGESZ_16M, 1), 72*360275b3SKumar Gala 73*360275b3SKumar Gala /* *I*G* - Flash, localbus */ 74*360275b3SKumar Gala /* This will be changed to *I*G* after relocation to RAM. */ 75*360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 76*360275b3SKumar Gala MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 77*360275b3SKumar Gala 0, 2, BOOKE_PAGESZ_256M, 1), 78*360275b3SKumar Gala 79*360275b3SKumar Gala /* *I*G* - PCI */ 80*360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 81*360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 82*360275b3SKumar Gala 0, 3, BOOKE_PAGESZ_1G, 1), 83*360275b3SKumar Gala 84*360275b3SKumar Gala /* *I*G* - PCI */ 85*360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 86*360275b3SKumar Gala CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 87*360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 88*360275b3SKumar Gala 0, 4, BOOKE_PAGESZ_256M, 1), 89*360275b3SKumar Gala 90*360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 91*360275b3SKumar Gala CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 92*360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 93*360275b3SKumar Gala 0, 5, BOOKE_PAGESZ_256M, 1), 94*360275b3SKumar Gala 95*360275b3SKumar Gala /* *I*G* - PCI I/O */ 96*360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 97*360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 98*360275b3SKumar Gala 0, 6, BOOKE_PAGESZ_256K, 1), 99*360275b3SKumar Gala 100*360275b3SKumar Gala /* Bman/Qman */ 101*360275b3SKumar Gala #ifdef CONFIG_SYS_BMAN_MEM_PHYS 102*360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 103*360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 104*360275b3SKumar Gala 0, 9, BOOKE_PAGESZ_1M, 1), 105*360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, 106*360275b3SKumar Gala CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, 107*360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 108*360275b3SKumar Gala 0, 10, BOOKE_PAGESZ_1M, 1), 109*360275b3SKumar Gala #endif 110*360275b3SKumar Gala #ifdef CONFIG_SYS_QMAN_MEM_PHYS 111*360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 112*360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 113*360275b3SKumar Gala 0, 11, BOOKE_PAGESZ_1M, 1), 114*360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, 115*360275b3SKumar Gala CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, 116*360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 117*360275b3SKumar Gala 0, 12, BOOKE_PAGESZ_1M, 1), 118*360275b3SKumar Gala #endif 119*360275b3SKumar Gala #ifdef CONFIG_SYS_DCSRBAR_PHYS 120*360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 121*360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 122*360275b3SKumar Gala 0, 13, BOOKE_PAGESZ_4M, 1), 123*360275b3SKumar Gala #endif 124*360275b3SKumar Gala #ifdef CONFIG_SYS_NAND_BASE 125*360275b3SKumar Gala /* 126*360275b3SKumar Gala * *I*G - NAND 127*360275b3SKumar Gala * entry 14 and 15 has been used hard coded, they will be disabled 128*360275b3SKumar Gala * in cpu_init_f, so we use entry 16 for nand. 129*360275b3SKumar Gala */ 130*360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 131*360275b3SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 132*360275b3SKumar Gala 0, 16, BOOKE_PAGESZ_1M, 1), 133*360275b3SKumar Gala #endif 134*360275b3SKumar Gala }; 135*360275b3SKumar Gala 136*360275b3SKumar Gala int num_tlb_entries = ARRAY_SIZE(tlb_table); 137