1360275b3SKumar Gala /* 2360275b3SKumar Gala * Copyright 2008-2011 Freescale Semiconductor, Inc. 3360275b3SKumar Gala * 4360275b3SKumar Gala * (C) Copyright 2000 5360275b3SKumar Gala * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6360275b3SKumar Gala * 7*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8360275b3SKumar Gala */ 9360275b3SKumar Gala 10360275b3SKumar Gala #include <common.h> 11360275b3SKumar Gala #include <asm/mmu.h> 12360275b3SKumar Gala 13360275b3SKumar Gala struct fsl_e_tlb_entry tlb_table[] = { 14360275b3SKumar Gala /* TLB 0 - for temp stack in cache */ 15360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 16360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS, 17360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 18360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 19360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 20360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 21360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 22360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 23360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 24360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 25360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 26360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 27360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 28360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 29360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 30360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 31f8bc7bb5SKumar Gala #ifdef CPLD_BASE 32f8bc7bb5SKumar Gala SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS, 33f8bc7bb5SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 34f8bc7bb5SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 35f8bc7bb5SKumar Gala #endif 36360275b3SKumar Gala 37f8bc7bb5SKumar Gala #ifdef PIXIS_BASE 38360275b3SKumar Gala SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, 39360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 40360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 41f8bc7bb5SKumar Gala #endif 42360275b3SKumar Gala 43360275b3SKumar Gala /* TLB 1 */ 44360275b3SKumar Gala /* *I*** - Covers boot page */ 45360275b3SKumar Gala #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 46360275b3SKumar Gala /* 47360275b3SKumar Gala * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 48360275b3SKumar Gala * SRAM is at 0xfff00000, it covered the 0xfffff000. 49360275b3SKumar Gala */ 50360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 51360275b3SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 52360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_1M, 1), 53461632bdSLiu Gang #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 54292dc6c5SLiu Gang /* 55461632bdSLiu Gang * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the 56292dc6c5SLiu Gang * space is at 0xfff00000, it covered the 0xfffff000. 57292dc6c5SLiu Gang */ 58461632bdSLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, 59461632bdSLiu Gang CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, 60292dc6c5SLiu Gang MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 61292dc6c5SLiu Gang 0, 0, BOOKE_PAGESZ_1M, 1), 62360275b3SKumar Gala #else 63360275b3SKumar Gala SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 64360275b3SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 65360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 1), 66360275b3SKumar Gala #endif 67360275b3SKumar Gala 68360275b3SKumar Gala /* *I*G* - CCSRBAR */ 69360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 70360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 71360275b3SKumar Gala 0, 1, BOOKE_PAGESZ_16M, 1), 72360275b3SKumar Gala 73360275b3SKumar Gala /* *I*G* - Flash, localbus */ 74360275b3SKumar Gala /* This will be changed to *I*G* after relocation to RAM. */ 75360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 76360275b3SKumar Gala MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 77360275b3SKumar Gala 0, 2, BOOKE_PAGESZ_256M, 1), 78360275b3SKumar Gala 79360275b3SKumar Gala /* *I*G* - PCI */ 80360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 81360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 82360275b3SKumar Gala 0, 3, BOOKE_PAGESZ_1G, 1), 83360275b3SKumar Gala 84360275b3SKumar Gala /* *I*G* - PCI */ 85360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 86360275b3SKumar Gala CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 87360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 88360275b3SKumar Gala 0, 4, BOOKE_PAGESZ_256M, 1), 89360275b3SKumar Gala 90360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 91360275b3SKumar Gala CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 92360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 93360275b3SKumar Gala 0, 5, BOOKE_PAGESZ_256M, 1), 94360275b3SKumar Gala 95360275b3SKumar Gala /* *I*G* - PCI I/O */ 96360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 97360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 98360275b3SKumar Gala 0, 6, BOOKE_PAGESZ_256K, 1), 99360275b3SKumar Gala 100360275b3SKumar Gala /* Bman/Qman */ 101360275b3SKumar Gala #ifdef CONFIG_SYS_BMAN_MEM_PHYS 102360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 103360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 104360275b3SKumar Gala 0, 9, BOOKE_PAGESZ_1M, 1), 105360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, 106360275b3SKumar Gala CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, 107360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 108360275b3SKumar Gala 0, 10, BOOKE_PAGESZ_1M, 1), 109360275b3SKumar Gala #endif 110360275b3SKumar Gala #ifdef CONFIG_SYS_QMAN_MEM_PHYS 111360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 112360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 113360275b3SKumar Gala 0, 11, BOOKE_PAGESZ_1M, 1), 114360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, 115360275b3SKumar Gala CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, 116360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 117360275b3SKumar Gala 0, 12, BOOKE_PAGESZ_1M, 1), 118360275b3SKumar Gala #endif 119360275b3SKumar Gala #ifdef CONFIG_SYS_DCSRBAR_PHYS 120360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 121360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 122360275b3SKumar Gala 0, 13, BOOKE_PAGESZ_4M, 1), 123360275b3SKumar Gala #endif 124360275b3SKumar Gala #ifdef CONFIG_SYS_NAND_BASE 125360275b3SKumar Gala /* 126360275b3SKumar Gala * *I*G - NAND 127360275b3SKumar Gala * entry 14 and 15 has been used hard coded, they will be disabled 128360275b3SKumar Gala * in cpu_init_f, so we use entry 16 for nand. 129360275b3SKumar Gala */ 130360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 131360275b3SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 132360275b3SKumar Gala 0, 16, BOOKE_PAGESZ_1M, 1), 133360275b3SKumar Gala #endif 134461632bdSLiu Gang #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 1353f1af81bSLiu Gang /* 136461632bdSLiu Gang * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for 137461632bdSLiu Gang * fetching ucode and ENV from master 1383f1af81bSLiu Gang */ 139461632bdSLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, 140461632bdSLiu Gang CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, 1413f1af81bSLiu Gang MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 1423f1af81bSLiu Gang 0, 17, BOOKE_PAGESZ_1M, 1), 1433f1af81bSLiu Gang #endif 144360275b3SKumar Gala }; 145360275b3SKumar Gala 146360275b3SKumar Gala int num_tlb_entries = ARRAY_SIZE(tlb_table); 147