1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2360275b3SKumar Gala /* 3360275b3SKumar Gala * Copyright 2008-2011 Freescale Semiconductor, Inc. 4360275b3SKumar Gala * 5360275b3SKumar Gala * (C) Copyright 2000 6360275b3SKumar Gala * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7360275b3SKumar Gala */ 8360275b3SKumar Gala 9360275b3SKumar Gala #include <common.h> 10360275b3SKumar Gala #include <asm/fsl_law.h> 11360275b3SKumar Gala #include <asm/mmu.h> 12360275b3SKumar Gala 13360275b3SKumar Gala struct law_entry law_table[] = { 14360275b3SKumar Gala SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), 15360275b3SKumar Gala #ifdef CONFIG_SYS_BMAN_MEM_PHYS 16360275b3SKumar Gala SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), 17360275b3SKumar Gala #endif 18360275b3SKumar Gala #ifdef CONFIG_SYS_QMAN_MEM_PHYS 19360275b3SKumar Gala SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), 20360275b3SKumar Gala #endif 21f8bc7bb5SKumar Gala #ifdef PIXIS_BASE_PHYS 22360275b3SKumar Gala SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), 23f8bc7bb5SKumar Gala #endif 24f8bc7bb5SKumar Gala #ifdef CPLD_BASE_PHYS 25f8bc7bb5SKumar Gala SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), 26f8bc7bb5SKumar Gala #endif 27360275b3SKumar Gala #ifdef CONFIG_SYS_DCSRBAR_PHYS 28360275b3SKumar Gala /* Limit DCSR to 32M to access NPC Trace Buffer */ 29360275b3SKumar Gala SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), 30360275b3SKumar Gala #endif 31360275b3SKumar Gala #ifdef CONFIG_SYS_NAND_BASE_PHYS 32360275b3SKumar Gala SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), 33360275b3SKumar Gala #endif 34360275b3SKumar Gala }; 35360275b3SKumar Gala 36360275b3SKumar Gala int num_law_entries = ARRAY_SIZE(law_table); 37