1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2014 Freescale Semiconductor 4 */ 5 6 #include <common.h> 7 #include <asm/io.h> 8 #include <fsl_csu.h> 9 #include <asm/arch/ns_access.h> 10 #include <asm/arch/fsl_serdes.h> 11 12 #ifdef CONFIG_ARCH_LS1021A 13 static struct csu_ns_dev ns_dev[] = { 14 { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, 15 { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, 16 { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, 17 { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, 18 { CSU_CSLX_OCRAM, CSU_ALL_RW }, 19 { CSU_CSLX_GIC, CSU_ALL_RW }, 20 { CSU_CSLX_PCIE1, CSU_ALL_RW }, 21 { CSU_CSLX_OCRAM2, CSU_ALL_RW }, 22 { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, 23 { CSU_CSLX_PCIE2, CSU_ALL_RW }, 24 { CSU_CSLX_SATA, CSU_ALL_RW }, 25 { CSU_CSLX_USB3, CSU_ALL_RW }, 26 { CSU_CSLX_SERDES, CSU_ALL_RW }, 27 { CSU_CSLX_QDMA, CSU_ALL_RW }, 28 { CSU_CSLX_LPUART2, CSU_ALL_RW }, 29 { CSU_CSLX_LPUART1, CSU_ALL_RW }, 30 { CSU_CSLX_LPUART4, CSU_ALL_RW }, 31 { CSU_CSLX_LPUART3, CSU_ALL_RW }, 32 { CSU_CSLX_LPUART6, CSU_ALL_RW }, 33 { CSU_CSLX_LPUART5, CSU_ALL_RW }, 34 { CSU_CSLX_DSPI2, CSU_ALL_RW }, 35 { CSU_CSLX_DSPI1, CSU_ALL_RW }, 36 { CSU_CSLX_QSPI, CSU_ALL_RW }, 37 { CSU_CSLX_ESDHC, CSU_ALL_RW }, 38 { CSU_CSLX_2D_ACE, CSU_ALL_RW }, 39 { CSU_CSLX_IFC, CSU_ALL_RW }, 40 { CSU_CSLX_I2C1, CSU_ALL_RW }, 41 { CSU_CSLX_USB2, CSU_ALL_RW }, 42 { CSU_CSLX_I2C3, CSU_ALL_RW }, 43 { CSU_CSLX_I2C2, CSU_ALL_RW }, 44 { CSU_CSLX_DUART2, CSU_ALL_RW }, 45 { CSU_CSLX_DUART1, CSU_ALL_RW }, 46 { CSU_CSLX_WDT2, CSU_ALL_RW }, 47 { CSU_CSLX_WDT1, CSU_ALL_RW }, 48 { CSU_CSLX_EDMA, CSU_ALL_RW }, 49 { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, 50 { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, 51 { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, 52 { CSU_CSLX_DDR, CSU_ALL_RW }, 53 { CSU_CSLX_QUICC, CSU_ALL_RW }, 54 { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, 55 { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, 56 { CSU_CSLX_SFP, CSU_ALL_RW }, 57 { CSU_CSLX_TMU, CSU_ALL_RW }, 58 { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, 59 { CSU_CSLX_RESERVED0, CSU_ALL_RW }, 60 { CSU_CSLX_ETSEC1, CSU_ALL_RW }, 61 { CSU_CSLX_SEC5_5, CSU_ALL_RW }, 62 { CSU_CSLX_ETSEC3, CSU_ALL_RW }, 63 { CSU_CSLX_ETSEC2, CSU_ALL_RW }, 64 { CSU_CSLX_GPIO2, CSU_ALL_RW }, 65 { CSU_CSLX_GPIO1, CSU_ALL_RW }, 66 { CSU_CSLX_GPIO4, CSU_ALL_RW }, 67 { CSU_CSLX_GPIO3, CSU_ALL_RW }, 68 { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, 69 { CSU_CSLX_CSU, CSU_ALL_RW }, 70 { CSU_CSLX_ASRC, CSU_ALL_RW }, 71 { CSU_CSLX_SPDIF, CSU_ALL_RW }, 72 { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, 73 { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, 74 { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, 75 { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, 76 { CSU_CSLX_SAI2, CSU_ALL_RW }, 77 { CSU_CSLX_SAI1, CSU_ALL_RW }, 78 { CSU_CSLX_SAI4, CSU_ALL_RW }, 79 { CSU_CSLX_SAI3, CSU_ALL_RW }, 80 { CSU_CSLX_FTM2, CSU_ALL_RW }, 81 { CSU_CSLX_FTM1, CSU_ALL_RW }, 82 { CSU_CSLX_FTM4, CSU_ALL_RW }, 83 { CSU_CSLX_FTM3, CSU_ALL_RW }, 84 { CSU_CSLX_FTM6, CSU_ALL_RW }, 85 { CSU_CSLX_FTM5, CSU_ALL_RW }, 86 { CSU_CSLX_FTM8, CSU_ALL_RW }, 87 { CSU_CSLX_FTM7, CSU_ALL_RW }, 88 { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, 89 { CSU_CSLX_EPU, CSU_ALL_RW }, 90 { CSU_CSLX_GDI, CSU_ALL_RW }, 91 { CSU_CSLX_DDI, CSU_ALL_RW }, 92 { CSU_CSLX_RESERVED1, CSU_ALL_RW }, 93 { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, 94 { CSU_CSLX_RESERVED2, CSU_ALL_RW }, 95 }; 96 97 #else 98 static struct csu_ns_dev ns_dev[] = { 99 {CSU_CSLX_PCIE2_IO, CSU_ALL_RW}, 100 {CSU_CSLX_PCIE1_IO, CSU_ALL_RW}, 101 {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW}, 102 {CSU_CSLX_IFC_MEM, CSU_ALL_RW}, 103 {CSU_CSLX_OCRAM, CSU_ALL_RW}, 104 {CSU_CSLX_GIC, CSU_ALL_RW}, 105 {CSU_CSLX_PCIE1, CSU_ALL_RW}, 106 {CSU_CSLX_OCRAM2, CSU_ALL_RW}, 107 {CSU_CSLX_QSPI_MEM, CSU_ALL_RW}, 108 {CSU_CSLX_PCIE2, CSU_ALL_RW}, 109 {CSU_CSLX_SATA, CSU_ALL_RW}, 110 {CSU_CSLX_USB1, CSU_ALL_RW}, 111 {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW}, 112 {CSU_CSLX_PCIE3, CSU_ALL_RW}, 113 {CSU_CSLX_PCIE3_IO, CSU_ALL_RW}, 114 {CSU_CSLX_USB3, CSU_ALL_RW}, 115 {CSU_CSLX_USB2, CSU_ALL_RW}, 116 {CSU_CSLX_PFE, CSU_ALL_RW}, 117 {CSU_CSLX_SERDES, CSU_ALL_RW}, 118 {CSU_CSLX_QDMA, CSU_ALL_RW}, 119 {CSU_CSLX_LPUART2, CSU_ALL_RW}, 120 {CSU_CSLX_LPUART1, CSU_ALL_RW}, 121 {CSU_CSLX_LPUART4, CSU_ALL_RW}, 122 {CSU_CSLX_LPUART3, CSU_ALL_RW}, 123 {CSU_CSLX_LPUART6, CSU_ALL_RW}, 124 {CSU_CSLX_LPUART5, CSU_ALL_RW}, 125 {CSU_CSLX_DSPI1, CSU_ALL_RW}, 126 {CSU_CSLX_QSPI, CSU_ALL_RW}, 127 {CSU_CSLX_ESDHC, CSU_ALL_RW}, 128 {CSU_CSLX_IFC, CSU_ALL_RW}, 129 {CSU_CSLX_I2C1, CSU_ALL_RW}, 130 {CSU_CSLX_I2C3, CSU_ALL_RW}, 131 {CSU_CSLX_I2C2, CSU_ALL_RW}, 132 {CSU_CSLX_DUART2, CSU_ALL_RW}, 133 {CSU_CSLX_DUART1, CSU_ALL_RW}, 134 {CSU_CSLX_WDT2, CSU_ALL_RW}, 135 {CSU_CSLX_WDT1, CSU_ALL_RW}, 136 {CSU_CSLX_EDMA, CSU_ALL_RW}, 137 {CSU_CSLX_SYS_CNT, CSU_ALL_RW}, 138 {CSU_CSLX_DMA_MUX2, CSU_ALL_RW}, 139 {CSU_CSLX_DMA_MUX1, CSU_ALL_RW}, 140 {CSU_CSLX_DDR, CSU_ALL_RW}, 141 {CSU_CSLX_QUICC, CSU_ALL_RW}, 142 {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW}, 143 {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW}, 144 {CSU_CSLX_SFP, CSU_ALL_RW}, 145 {CSU_CSLX_TMU, CSU_ALL_RW}, 146 {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW}, 147 {CSU_CSLX_SCFG, CSU_ALL_RW}, 148 {CSU_CSLX_FM, CSU_ALL_RW}, 149 {CSU_CSLX_SEC5_5, CSU_ALL_RW}, 150 {CSU_CSLX_BM, CSU_ALL_RW}, 151 {CSU_CSLX_QM, CSU_ALL_RW}, 152 {CSU_CSLX_GPIO2, CSU_ALL_RW}, 153 {CSU_CSLX_GPIO1, CSU_ALL_RW}, 154 {CSU_CSLX_GPIO4, CSU_ALL_RW}, 155 {CSU_CSLX_GPIO3, CSU_ALL_RW}, 156 {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW}, 157 {CSU_CSLX_CSU, CSU_ALL_RW}, 158 {CSU_CSLX_IIC4, CSU_ALL_RW}, 159 {CSU_CSLX_WDT4, CSU_ALL_RW}, 160 {CSU_CSLX_WDT3, CSU_ALL_RW}, 161 {CSU_CSLX_ESDHC2, CSU_ALL_RW}, 162 {CSU_CSLX_WDT5, CSU_ALL_RW}, 163 {CSU_CSLX_SAI2, CSU_ALL_RW}, 164 {CSU_CSLX_SAI1, CSU_ALL_RW}, 165 {CSU_CSLX_SAI4, CSU_ALL_RW}, 166 {CSU_CSLX_SAI3, CSU_ALL_RW}, 167 {CSU_CSLX_FTM2, CSU_ALL_RW}, 168 {CSU_CSLX_FTM1, CSU_ALL_RW}, 169 {CSU_CSLX_FTM4, CSU_ALL_RW}, 170 {CSU_CSLX_FTM3, CSU_ALL_RW}, 171 {CSU_CSLX_FTM6, CSU_ALL_RW}, 172 {CSU_CSLX_FTM5, CSU_ALL_RW}, 173 {CSU_CSLX_FTM8, CSU_ALL_RW}, 174 {CSU_CSLX_FTM7, CSU_ALL_RW}, 175 {CSU_CSLX_DSCR, CSU_ALL_RW}, 176 }; 177 #endif 178 179 void set_devices_ns_access(unsigned long index, u16 val) 180 { 181 u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; 182 u32 *reg; 183 uint32_t tmp; 184 185 reg = base + index / 2; 186 tmp = in_be32(reg); 187 if (index % 2 == 0) { 188 tmp &= 0x0000ffff; 189 tmp |= val << 16; 190 } else { 191 tmp &= 0xffff0000; 192 tmp |= val; 193 } 194 195 out_be32(reg, tmp); 196 } 197 198 static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) 199 { 200 int i; 201 202 for (i = 0; i < num; i++) 203 set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val); 204 } 205 206 void enable_layerscape_ns_access(void) 207 { 208 #ifdef CONFIG_ARM64 209 if (current_el() == 3) 210 #endif 211 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); 212 } 213 214 void set_pcie_ns_access(int pcie, u16 val) 215 { 216 switch (pcie) { 217 #ifdef CONFIG_PCIE1 218 case PCIE1: 219 set_devices_ns_access(CSU_CSLX_PCIE1, val); 220 set_devices_ns_access(CSU_CSLX_PCIE1_IO, val); 221 return; 222 #endif 223 #ifdef CONFIG_PCIE2 224 case PCIE2: 225 set_devices_ns_access(CSU_CSLX_PCIE2, val); 226 set_devices_ns_access(CSU_CSLX_PCIE2_IO, val); 227 return; 228 #endif 229 #ifdef CONFIG_PCIE3 230 case PCIE3: 231 set_devices_ns_access(CSU_CSLX_PCIE3, val); 232 set_devices_ns_access(CSU_CSLX_PCIE3_IO, val); 233 return; 234 #endif 235 default: 236 debug("The PCIE%d doesn't exist!\n", pcie); 237 return; 238 } 239 } 240