183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2e87f3b30SXiubo Li /* 3e87f3b30SXiubo Li * Copyright 2014 Freescale Semiconductor 4e87f3b30SXiubo Li */ 5e87f3b30SXiubo Li 6e87f3b30SXiubo Li #include <common.h> 7e87f3b30SXiubo Li #include <asm/io.h> 8435acd83SMingkai Hu #include <fsl_csu.h> 9e87f3b30SXiubo Li #include <asm/arch/ns_access.h> 10664b6520SHou Zhiqiang #include <asm/arch/fsl_serdes.h> 11e87f3b30SXiubo Li 12*cd358554SRan Wang #ifdef CONFIG_ARCH_LS1021A 13*cd358554SRan Wang static struct csu_ns_dev ns_dev[] = { 14*cd358554SRan Wang { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, 15*cd358554SRan Wang { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, 16*cd358554SRan Wang { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, 17*cd358554SRan Wang { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, 18*cd358554SRan Wang { CSU_CSLX_OCRAM, CSU_ALL_RW }, 19*cd358554SRan Wang { CSU_CSLX_GIC, CSU_ALL_RW }, 20*cd358554SRan Wang { CSU_CSLX_PCIE1, CSU_ALL_RW }, 21*cd358554SRan Wang { CSU_CSLX_OCRAM2, CSU_ALL_RW }, 22*cd358554SRan Wang { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, 23*cd358554SRan Wang { CSU_CSLX_PCIE2, CSU_ALL_RW }, 24*cd358554SRan Wang { CSU_CSLX_SATA, CSU_ALL_RW }, 25*cd358554SRan Wang { CSU_CSLX_USB3, CSU_ALL_RW }, 26*cd358554SRan Wang { CSU_CSLX_SERDES, CSU_ALL_RW }, 27*cd358554SRan Wang { CSU_CSLX_QDMA, CSU_ALL_RW }, 28*cd358554SRan Wang { CSU_CSLX_LPUART2, CSU_ALL_RW }, 29*cd358554SRan Wang { CSU_CSLX_LPUART1, CSU_ALL_RW }, 30*cd358554SRan Wang { CSU_CSLX_LPUART4, CSU_ALL_RW }, 31*cd358554SRan Wang { CSU_CSLX_LPUART3, CSU_ALL_RW }, 32*cd358554SRan Wang { CSU_CSLX_LPUART6, CSU_ALL_RW }, 33*cd358554SRan Wang { CSU_CSLX_LPUART5, CSU_ALL_RW }, 34*cd358554SRan Wang { CSU_CSLX_DSPI2, CSU_ALL_RW }, 35*cd358554SRan Wang { CSU_CSLX_DSPI1, CSU_ALL_RW }, 36*cd358554SRan Wang { CSU_CSLX_QSPI, CSU_ALL_RW }, 37*cd358554SRan Wang { CSU_CSLX_ESDHC, CSU_ALL_RW }, 38*cd358554SRan Wang { CSU_CSLX_2D_ACE, CSU_ALL_RW }, 39*cd358554SRan Wang { CSU_CSLX_IFC, CSU_ALL_RW }, 40*cd358554SRan Wang { CSU_CSLX_I2C1, CSU_ALL_RW }, 41*cd358554SRan Wang { CSU_CSLX_USB2, CSU_ALL_RW }, 42*cd358554SRan Wang { CSU_CSLX_I2C3, CSU_ALL_RW }, 43*cd358554SRan Wang { CSU_CSLX_I2C2, CSU_ALL_RW }, 44*cd358554SRan Wang { CSU_CSLX_DUART2, CSU_ALL_RW }, 45*cd358554SRan Wang { CSU_CSLX_DUART1, CSU_ALL_RW }, 46*cd358554SRan Wang { CSU_CSLX_WDT2, CSU_ALL_RW }, 47*cd358554SRan Wang { CSU_CSLX_WDT1, CSU_ALL_RW }, 48*cd358554SRan Wang { CSU_CSLX_EDMA, CSU_ALL_RW }, 49*cd358554SRan Wang { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, 50*cd358554SRan Wang { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, 51*cd358554SRan Wang { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, 52*cd358554SRan Wang { CSU_CSLX_DDR, CSU_ALL_RW }, 53*cd358554SRan Wang { CSU_CSLX_QUICC, CSU_ALL_RW }, 54*cd358554SRan Wang { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, 55*cd358554SRan Wang { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, 56*cd358554SRan Wang { CSU_CSLX_SFP, CSU_ALL_RW }, 57*cd358554SRan Wang { CSU_CSLX_TMU, CSU_ALL_RW }, 58*cd358554SRan Wang { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, 59*cd358554SRan Wang { CSU_CSLX_RESERVED0, CSU_ALL_RW }, 60*cd358554SRan Wang { CSU_CSLX_ETSEC1, CSU_ALL_RW }, 61*cd358554SRan Wang { CSU_CSLX_SEC5_5, CSU_ALL_RW }, 62*cd358554SRan Wang { CSU_CSLX_ETSEC3, CSU_ALL_RW }, 63*cd358554SRan Wang { CSU_CSLX_ETSEC2, CSU_ALL_RW }, 64*cd358554SRan Wang { CSU_CSLX_GPIO2, CSU_ALL_RW }, 65*cd358554SRan Wang { CSU_CSLX_GPIO1, CSU_ALL_RW }, 66*cd358554SRan Wang { CSU_CSLX_GPIO4, CSU_ALL_RW }, 67*cd358554SRan Wang { CSU_CSLX_GPIO3, CSU_ALL_RW }, 68*cd358554SRan Wang { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, 69*cd358554SRan Wang { CSU_CSLX_CSU, CSU_ALL_RW }, 70*cd358554SRan Wang { CSU_CSLX_ASRC, CSU_ALL_RW }, 71*cd358554SRan Wang { CSU_CSLX_SPDIF, CSU_ALL_RW }, 72*cd358554SRan Wang { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, 73*cd358554SRan Wang { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, 74*cd358554SRan Wang { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, 75*cd358554SRan Wang { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, 76*cd358554SRan Wang { CSU_CSLX_SAI2, CSU_ALL_RW }, 77*cd358554SRan Wang { CSU_CSLX_SAI1, CSU_ALL_RW }, 78*cd358554SRan Wang { CSU_CSLX_SAI4, CSU_ALL_RW }, 79*cd358554SRan Wang { CSU_CSLX_SAI3, CSU_ALL_RW }, 80*cd358554SRan Wang { CSU_CSLX_FTM2, CSU_ALL_RW }, 81*cd358554SRan Wang { CSU_CSLX_FTM1, CSU_ALL_RW }, 82*cd358554SRan Wang { CSU_CSLX_FTM4, CSU_ALL_RW }, 83*cd358554SRan Wang { CSU_CSLX_FTM3, CSU_ALL_RW }, 84*cd358554SRan Wang { CSU_CSLX_FTM6, CSU_ALL_RW }, 85*cd358554SRan Wang { CSU_CSLX_FTM5, CSU_ALL_RW }, 86*cd358554SRan Wang { CSU_CSLX_FTM8, CSU_ALL_RW }, 87*cd358554SRan Wang { CSU_CSLX_FTM7, CSU_ALL_RW }, 88*cd358554SRan Wang { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, 89*cd358554SRan Wang { CSU_CSLX_EPU, CSU_ALL_RW }, 90*cd358554SRan Wang { CSU_CSLX_GDI, CSU_ALL_RW }, 91*cd358554SRan Wang { CSU_CSLX_DDI, CSU_ALL_RW }, 92*cd358554SRan Wang { CSU_CSLX_RESERVED1, CSU_ALL_RW }, 93*cd358554SRan Wang { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, 94*cd358554SRan Wang { CSU_CSLX_RESERVED2, CSU_ALL_RW }, 95*cd358554SRan Wang }; 96*cd358554SRan Wang 97*cd358554SRan Wang #else 98*cd358554SRan Wang static struct csu_ns_dev ns_dev[] = { 99*cd358554SRan Wang {CSU_CSLX_PCIE2_IO, CSU_ALL_RW}, 100*cd358554SRan Wang {CSU_CSLX_PCIE1_IO, CSU_ALL_RW}, 101*cd358554SRan Wang {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW}, 102*cd358554SRan Wang {CSU_CSLX_IFC_MEM, CSU_ALL_RW}, 103*cd358554SRan Wang {CSU_CSLX_OCRAM, CSU_ALL_RW}, 104*cd358554SRan Wang {CSU_CSLX_GIC, CSU_ALL_RW}, 105*cd358554SRan Wang {CSU_CSLX_PCIE1, CSU_ALL_RW}, 106*cd358554SRan Wang {CSU_CSLX_OCRAM2, CSU_ALL_RW}, 107*cd358554SRan Wang {CSU_CSLX_QSPI_MEM, CSU_ALL_RW}, 108*cd358554SRan Wang {CSU_CSLX_PCIE2, CSU_ALL_RW}, 109*cd358554SRan Wang {CSU_CSLX_SATA, CSU_ALL_RW}, 110*cd358554SRan Wang {CSU_CSLX_USB1, CSU_ALL_RW}, 111*cd358554SRan Wang {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW}, 112*cd358554SRan Wang {CSU_CSLX_PCIE3, CSU_ALL_RW}, 113*cd358554SRan Wang {CSU_CSLX_PCIE3_IO, CSU_ALL_RW}, 114*cd358554SRan Wang {CSU_CSLX_USB3, CSU_ALL_RW}, 115*cd358554SRan Wang {CSU_CSLX_USB2, CSU_ALL_RW}, 116*cd358554SRan Wang {CSU_CSLX_PFE, CSU_ALL_RW}, 117*cd358554SRan Wang {CSU_CSLX_SERDES, CSU_ALL_RW}, 118*cd358554SRan Wang {CSU_CSLX_QDMA, CSU_ALL_RW}, 119*cd358554SRan Wang {CSU_CSLX_LPUART2, CSU_ALL_RW}, 120*cd358554SRan Wang {CSU_CSLX_LPUART1, CSU_ALL_RW}, 121*cd358554SRan Wang {CSU_CSLX_LPUART4, CSU_ALL_RW}, 122*cd358554SRan Wang {CSU_CSLX_LPUART3, CSU_ALL_RW}, 123*cd358554SRan Wang {CSU_CSLX_LPUART6, CSU_ALL_RW}, 124*cd358554SRan Wang {CSU_CSLX_LPUART5, CSU_ALL_RW}, 125*cd358554SRan Wang {CSU_CSLX_DSPI1, CSU_ALL_RW}, 126*cd358554SRan Wang {CSU_CSLX_QSPI, CSU_ALL_RW}, 127*cd358554SRan Wang {CSU_CSLX_ESDHC, CSU_ALL_RW}, 128*cd358554SRan Wang {CSU_CSLX_IFC, CSU_ALL_RW}, 129*cd358554SRan Wang {CSU_CSLX_I2C1, CSU_ALL_RW}, 130*cd358554SRan Wang {CSU_CSLX_I2C3, CSU_ALL_RW}, 131*cd358554SRan Wang {CSU_CSLX_I2C2, CSU_ALL_RW}, 132*cd358554SRan Wang {CSU_CSLX_DUART2, CSU_ALL_RW}, 133*cd358554SRan Wang {CSU_CSLX_DUART1, CSU_ALL_RW}, 134*cd358554SRan Wang {CSU_CSLX_WDT2, CSU_ALL_RW}, 135*cd358554SRan Wang {CSU_CSLX_WDT1, CSU_ALL_RW}, 136*cd358554SRan Wang {CSU_CSLX_EDMA, CSU_ALL_RW}, 137*cd358554SRan Wang {CSU_CSLX_SYS_CNT, CSU_ALL_RW}, 138*cd358554SRan Wang {CSU_CSLX_DMA_MUX2, CSU_ALL_RW}, 139*cd358554SRan Wang {CSU_CSLX_DMA_MUX1, CSU_ALL_RW}, 140*cd358554SRan Wang {CSU_CSLX_DDR, CSU_ALL_RW}, 141*cd358554SRan Wang {CSU_CSLX_QUICC, CSU_ALL_RW}, 142*cd358554SRan Wang {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW}, 143*cd358554SRan Wang {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW}, 144*cd358554SRan Wang {CSU_CSLX_SFP, CSU_ALL_RW}, 145*cd358554SRan Wang {CSU_CSLX_TMU, CSU_ALL_RW}, 146*cd358554SRan Wang {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW}, 147*cd358554SRan Wang {CSU_CSLX_SCFG, CSU_ALL_RW}, 148*cd358554SRan Wang {CSU_CSLX_FM, CSU_ALL_RW}, 149*cd358554SRan Wang {CSU_CSLX_SEC5_5, CSU_ALL_RW}, 150*cd358554SRan Wang {CSU_CSLX_BM, CSU_ALL_RW}, 151*cd358554SRan Wang {CSU_CSLX_QM, CSU_ALL_RW}, 152*cd358554SRan Wang {CSU_CSLX_GPIO2, CSU_ALL_RW}, 153*cd358554SRan Wang {CSU_CSLX_GPIO1, CSU_ALL_RW}, 154*cd358554SRan Wang {CSU_CSLX_GPIO4, CSU_ALL_RW}, 155*cd358554SRan Wang {CSU_CSLX_GPIO3, CSU_ALL_RW}, 156*cd358554SRan Wang {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW}, 157*cd358554SRan Wang {CSU_CSLX_CSU, CSU_ALL_RW}, 158*cd358554SRan Wang {CSU_CSLX_IIC4, CSU_ALL_RW}, 159*cd358554SRan Wang {CSU_CSLX_WDT4, CSU_ALL_RW}, 160*cd358554SRan Wang {CSU_CSLX_WDT3, CSU_ALL_RW}, 161*cd358554SRan Wang {CSU_CSLX_ESDHC2, CSU_ALL_RW}, 162*cd358554SRan Wang {CSU_CSLX_WDT5, CSU_ALL_RW}, 163*cd358554SRan Wang {CSU_CSLX_SAI2, CSU_ALL_RW}, 164*cd358554SRan Wang {CSU_CSLX_SAI1, CSU_ALL_RW}, 165*cd358554SRan Wang {CSU_CSLX_SAI4, CSU_ALL_RW}, 166*cd358554SRan Wang {CSU_CSLX_SAI3, CSU_ALL_RW}, 167*cd358554SRan Wang {CSU_CSLX_FTM2, CSU_ALL_RW}, 168*cd358554SRan Wang {CSU_CSLX_FTM1, CSU_ALL_RW}, 169*cd358554SRan Wang {CSU_CSLX_FTM4, CSU_ALL_RW}, 170*cd358554SRan Wang {CSU_CSLX_FTM3, CSU_ALL_RW}, 171*cd358554SRan Wang {CSU_CSLX_FTM6, CSU_ALL_RW}, 172*cd358554SRan Wang {CSU_CSLX_FTM5, CSU_ALL_RW}, 173*cd358554SRan Wang {CSU_CSLX_FTM8, CSU_ALL_RW}, 174*cd358554SRan Wang {CSU_CSLX_FTM7, CSU_ALL_RW}, 175*cd358554SRan Wang {CSU_CSLX_DSCR, CSU_ALL_RW}, 176*cd358554SRan Wang }; 177*cd358554SRan Wang #endif 178*cd358554SRan Wang 179acb90e83SHou Zhiqiang void set_devices_ns_access(unsigned long index, u16 val) 180e87f3b30SXiubo Li { 181e87f3b30SXiubo Li u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; 182e87f3b30SXiubo Li u32 *reg; 183c37fdbdbSHou Zhiqiang uint32_t tmp; 184c37fdbdbSHou Zhiqiang 185acb90e83SHou Zhiqiang reg = base + index / 2; 186c37fdbdbSHou Zhiqiang tmp = in_be32(reg); 187acb90e83SHou Zhiqiang if (index % 2 == 0) { 188c37fdbdbSHou Zhiqiang tmp &= 0x0000ffff; 189c37fdbdbSHou Zhiqiang tmp |= val << 16; 190c37fdbdbSHou Zhiqiang } else { 191c37fdbdbSHou Zhiqiang tmp &= 0xffff0000; 192c37fdbdbSHou Zhiqiang tmp |= val; 193c37fdbdbSHou Zhiqiang } 194c37fdbdbSHou Zhiqiang 195c37fdbdbSHou Zhiqiang out_be32(reg, tmp); 196c37fdbdbSHou Zhiqiang } 197c37fdbdbSHou Zhiqiang 198c37fdbdbSHou Zhiqiang static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) 199c37fdbdbSHou Zhiqiang { 200e87f3b30SXiubo Li int i; 201e87f3b30SXiubo Li 202c37fdbdbSHou Zhiqiang for (i = 0; i < num; i++) 203acb90e83SHou Zhiqiang set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val); 204e87f3b30SXiubo Li } 205435acd83SMingkai Hu 206435acd83SMingkai Hu void enable_layerscape_ns_access(void) 207435acd83SMingkai Hu { 208399e2bb6SYork Sun #ifdef CONFIG_ARM64 209399e2bb6SYork Sun if (current_el() == 3) 210399e2bb6SYork Sun #endif 211435acd83SMingkai Hu enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); 212435acd83SMingkai Hu } 213664b6520SHou Zhiqiang 214664b6520SHou Zhiqiang void set_pcie_ns_access(int pcie, u16 val) 215664b6520SHou Zhiqiang { 216664b6520SHou Zhiqiang switch (pcie) { 217664b6520SHou Zhiqiang #ifdef CONFIG_PCIE1 218664b6520SHou Zhiqiang case PCIE1: 219acb90e83SHou Zhiqiang set_devices_ns_access(CSU_CSLX_PCIE1, val); 220acb90e83SHou Zhiqiang set_devices_ns_access(CSU_CSLX_PCIE1_IO, val); 221664b6520SHou Zhiqiang return; 222664b6520SHou Zhiqiang #endif 223664b6520SHou Zhiqiang #ifdef CONFIG_PCIE2 224664b6520SHou Zhiqiang case PCIE2: 225acb90e83SHou Zhiqiang set_devices_ns_access(CSU_CSLX_PCIE2, val); 226acb90e83SHou Zhiqiang set_devices_ns_access(CSU_CSLX_PCIE2_IO, val); 227664b6520SHou Zhiqiang return; 228664b6520SHou Zhiqiang #endif 229664b6520SHou Zhiqiang #ifdef CONFIG_PCIE3 230664b6520SHou Zhiqiang case PCIE3: 231acb90e83SHou Zhiqiang set_devices_ns_access(CSU_CSLX_PCIE3, val); 232acb90e83SHou Zhiqiang set_devices_ns_access(CSU_CSLX_PCIE3_IO, val); 233664b6520SHou Zhiqiang return; 234664b6520SHou Zhiqiang #endif 235664b6520SHou Zhiqiang default: 236664b6520SHou Zhiqiang debug("The PCIE%d doesn't exist!\n", pcie); 237664b6520SHou Zhiqiang return; 238664b6520SHou Zhiqiang } 239664b6520SHou Zhiqiang } 240