1e87f3b30SXiubo Li /* 2e87f3b30SXiubo Li * Copyright 2014 Freescale Semiconductor 3e87f3b30SXiubo Li * 4e87f3b30SXiubo Li * SPDX-License-Identifier: GPL-2.0+ 5e87f3b30SXiubo Li */ 6e87f3b30SXiubo Li 7e87f3b30SXiubo Li #include <common.h> 8e87f3b30SXiubo Li #include <asm/io.h> 9435acd83SMingkai Hu #include <fsl_csu.h> 10e87f3b30SXiubo Li #include <asm/arch/ns_access.h> 11664b6520SHou Zhiqiang #include <asm/arch/fsl_serdes.h> 12e87f3b30SXiubo Li 13*acb90e83SHou Zhiqiang void set_devices_ns_access(unsigned long index, u16 val) 14e87f3b30SXiubo Li { 15e87f3b30SXiubo Li u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; 16e87f3b30SXiubo Li u32 *reg; 17c37fdbdbSHou Zhiqiang uint32_t tmp; 18c37fdbdbSHou Zhiqiang 19*acb90e83SHou Zhiqiang reg = base + index / 2; 20c37fdbdbSHou Zhiqiang tmp = in_be32(reg); 21*acb90e83SHou Zhiqiang if (index % 2 == 0) { 22c37fdbdbSHou Zhiqiang tmp &= 0x0000ffff; 23c37fdbdbSHou Zhiqiang tmp |= val << 16; 24c37fdbdbSHou Zhiqiang } else { 25c37fdbdbSHou Zhiqiang tmp &= 0xffff0000; 26c37fdbdbSHou Zhiqiang tmp |= val; 27c37fdbdbSHou Zhiqiang } 28c37fdbdbSHou Zhiqiang 29c37fdbdbSHou Zhiqiang out_be32(reg, tmp); 30c37fdbdbSHou Zhiqiang } 31c37fdbdbSHou Zhiqiang 32c37fdbdbSHou Zhiqiang static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) 33c37fdbdbSHou Zhiqiang { 34e87f3b30SXiubo Li int i; 35e87f3b30SXiubo Li 36c37fdbdbSHou Zhiqiang for (i = 0; i < num; i++) 37*acb90e83SHou Zhiqiang set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val); 38e87f3b30SXiubo Li } 39435acd83SMingkai Hu 40435acd83SMingkai Hu void enable_layerscape_ns_access(void) 41435acd83SMingkai Hu { 42399e2bb6SYork Sun #ifdef CONFIG_ARM64 43399e2bb6SYork Sun if (current_el() == 3) 44399e2bb6SYork Sun #endif 45435acd83SMingkai Hu enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); 46435acd83SMingkai Hu } 47664b6520SHou Zhiqiang 48664b6520SHou Zhiqiang void set_pcie_ns_access(int pcie, u16 val) 49664b6520SHou Zhiqiang { 50664b6520SHou Zhiqiang switch (pcie) { 51664b6520SHou Zhiqiang #ifdef CONFIG_PCIE1 52664b6520SHou Zhiqiang case PCIE1: 53*acb90e83SHou Zhiqiang set_devices_ns_access(CSU_CSLX_PCIE1, val); 54*acb90e83SHou Zhiqiang set_devices_ns_access(CSU_CSLX_PCIE1_IO, val); 55664b6520SHou Zhiqiang return; 56664b6520SHou Zhiqiang #endif 57664b6520SHou Zhiqiang #ifdef CONFIG_PCIE2 58664b6520SHou Zhiqiang case PCIE2: 59*acb90e83SHou Zhiqiang set_devices_ns_access(CSU_CSLX_PCIE2, val); 60*acb90e83SHou Zhiqiang set_devices_ns_access(CSU_CSLX_PCIE2_IO, val); 61664b6520SHou Zhiqiang return; 62664b6520SHou Zhiqiang #endif 63664b6520SHou Zhiqiang #ifdef CONFIG_PCIE3 64664b6520SHou Zhiqiang case PCIE3: 65*acb90e83SHou Zhiqiang set_devices_ns_access(CSU_CSLX_PCIE3, val); 66*acb90e83SHou Zhiqiang set_devices_ns_access(CSU_CSLX_PCIE3_IO, val); 67664b6520SHou Zhiqiang return; 68664b6520SHou Zhiqiang #endif 69664b6520SHou Zhiqiang default: 70664b6520SHou Zhiqiang debug("The PCIE%d doesn't exist!\n", pcie); 71664b6520SHou Zhiqiang return; 72664b6520SHou Zhiqiang } 73664b6520SHou Zhiqiang } 74