1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <asm/immap_85xx.h>
8 #include "sleep.h"
9 #ifdef CONFIG_U_QE
10 #include <fsl_qe.h>
11 #endif
12 
13 DECLARE_GLOBAL_DATA_PTR;
14 
15 void __weak board_mem_sleep_setup(void)
16 {
17 }
18 
19 void __weak board_sleep_prepare(void)
20 {
21 }
22 
23 bool is_warm_boot(void)
24 {
25 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
26 
27 	if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR)
28 		return 1;
29 
30 	return 0;
31 }
32 
33 void fsl_dp_disable_console(void)
34 {
35 	gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
36 }
37 
38 /*
39  * When wakeup from deep sleep, the first 128 bytes space
40  * will be used to do DDR training which corrupts the data
41  * in there. This function will restore them.
42  */
43 static void dp_ddr_restore(void)
44 {
45 	u64 *src, *dst;
46 	int i;
47 	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
48 
49 	/* get the address of ddr date from SPARECR3 */
50 	src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
51 	dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
52 
53 	for (i = 0; i < DDR_BUFF_LEN / 8; i++)
54 		*dst-- = *src--;
55 
56 	flush_dcache();
57 }
58 
59 static void dp_resume_prepare(void)
60 {
61 	dp_ddr_restore();
62 
63 	board_sleep_prepare();
64 
65 	l2cache_init();
66 #if defined(CONFIG_RAMBOOT_PBL)
67 	disable_cpc_sram();
68 #endif
69 	enable_cpc();
70 
71 #ifdef CONFIG_U_QE
72 	u_qe_resume();
73 #endif
74 
75 }
76 
77 int fsl_dp_resume(void)
78 {
79 	u32 start_addr;
80 	void (*kernel_resume)(void);
81 	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
82 
83 	if (!is_warm_boot())
84 		return 0;
85 
86 	dp_resume_prepare();
87 
88 	/* Get the entry address and jump to kernel */
89 	start_addr = in_be32(&scfg->sparecr[1]);
90 	debug("Entry address is 0x%08x\n", start_addr);
91 	kernel_resume = (void (*)(void))start_addr;
92 	kernel_resume();
93 
94 	return 0;
95 }
96