1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * Author: Shaveta Leekha <shaveta@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __IDT8T49N222A_SERDES_CLK_H_ 9 #define __IDT8T49N222A_SERDES_CLK_H_ 1 10 11 #include <common.h> 12 #include <i2c.h> 13 #include "qixis.h" 14 #include "../b4860qds/b4860qds_qixis.h" 15 #include <errno.h> 16 17 #define NUM_IDT_REGS 23 18 #define NUM_IDT_REGS_FEEDBACK 12 19 #define NUM_IDT_REGS_156_25 11 20 21 /* CLK */ 22 enum serdes_refclk { 23 SERDES_REFCLK_100, /* refclk 100Mhz */ 24 SERDES_REFCLK_122_88, /* refclk 122.88Mhz */ 25 SERDES_REFCLK_125, /* refclk 125Mhz */ 26 SERDES_REFCLK_156_25, /* refclk 156.25Mhz */ 27 SERDES_REFCLK_NONE = -1, 28 }; 29 30 /* configuration values for IDT registers for Output Refclks: 31 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz 32 */ 33 static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00}, 34 {0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00}, 35 {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00}, 36 {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00}, 37 {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12}, 38 {0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08}, 39 {0x16, 0xA0} }; 40 41 42 /* configuration values for IDT registers for Output Refclks: 43 * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz 44 */ 45 static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00}, 46 {0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00}, 47 {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00}, 48 {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00}, 49 {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14}, 50 {0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08}, 51 {0x16, 0xA0} }; 52 53 /* Reconfiguration values for some of IDT registers for 54 * Output Refclks: 55 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz 56 * and with feedback as 1 57 */ 58 static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7}, 59 {0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07}, 60 {0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B}, 61 {0x14, 0x00}, {0x15, 0xE8} }; 62 63 /* configuration values for IDT registers for Output Refclks: 64 * Refclk1 : 156.25MHz Refclk2 : 156.25MHz 65 */ 66 static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, 67 {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, 68 {0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, 69 {0x15, 0xE8} }; 70 71 /* configuration values for IDT registers for Output Refclks: 72 * Refclk1 : 100MHz Refclk2 : 156.25MHz 73 */ 74 static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, 75 {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, 76 {0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, 77 {0x15, 0xE8} }; 78 79 /* configuration values for IDT registers for Output Refclks: 80 * Refclk1 : 125MHz Refclk2 : 156.25MHz 81 */ 82 static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, 83 {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, 84 {0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, 85 {0x15, 0xE8} }; 86 87 /* configuration values for IDT registers for Output Refclks: 88 * Refclk1 : 156.25MHz Refclk2 : 100MHz 89 */ 90 static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03}, 91 {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, 92 {0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C}, 93 {0x15, 0xE8} }; 94 95 /* configuration values for IDT registers for Output Refclks: 96 * Refclk1 : 156.25MHz Refclk2 : 125MHz 97 */ 98 static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03}, 99 {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, 100 {0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C}, 101 {0x15, 0xE8} }; 102 103 int set_serdes_refclk(u8 idt_addr, u8 serdes_num, 104 enum serdes_refclk refclk1, 105 enum serdes_refclk refclk2, u8 feedback); 106 107 #endif /*__IDT8T49N222A_SERDES_CLK_H_ */ 108