1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * Author: Shaveta Leekha <shaveta@freescale.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21 #ifndef __IDT8T49N222A_SERDES_CLK_H_ 22 #define __IDT8T49N222A_SERDES_CLK_H_ 1 23 24 #include <common.h> 25 #include <i2c.h> 26 #include "qixis.h" 27 #include "../b4860qds/b4860qds_qixis.h" 28 #include <errno.h> 29 30 #define NUM_IDT_REGS 23 31 #define NUM_IDT_REGS_FEEDBACK 12 32 #define NUM_IDT_REGS_156_25 11 33 34 /* CLK */ 35 enum serdes_refclk { 36 SERDES_REFCLK_100, /* refclk 100Mhz */ 37 SERDES_REFCLK_122_88, /* refclk 122.88Mhz */ 38 SERDES_REFCLK_125, /* refclk 125Mhz */ 39 SERDES_REFCLK_156_25, /* refclk 156.25Mhz */ 40 SERDES_REFCLK_NONE = -1, 41 }; 42 43 /* configuration values for IDT registers for Output Refclks: 44 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz 45 */ 46 static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00}, 47 {0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00}, 48 {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00}, 49 {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00}, 50 {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12}, 51 {0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08}, 52 {0x16, 0xA0} }; 53 54 55 /* configuration values for IDT registers for Output Refclks: 56 * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz 57 */ 58 static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00}, 59 {0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00}, 60 {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00}, 61 {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00}, 62 {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14}, 63 {0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08}, 64 {0x16, 0xA0} }; 65 66 /* Reconfiguration values for some of IDT registers for 67 * Output Refclks: 68 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz 69 * and with feedback as 1 70 */ 71 static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7}, 72 {0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07}, 73 {0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B}, 74 {0x14, 0x00}, {0x15, 0xE8} }; 75 76 /* configuration values for IDT registers for Output Refclks: 77 * Refclk1 : 156.25MHz Refclk2 : 156.25MHz 78 */ 79 static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, 80 {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, 81 {0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, 82 {0x15, 0xE8} }; 83 84 /* configuration values for IDT registers for Output Refclks: 85 * Refclk1 : 100MHz Refclk2 : 156.25MHz 86 */ 87 static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, 88 {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, 89 {0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, 90 {0x15, 0xE8} }; 91 92 /* configuration values for IDT registers for Output Refclks: 93 * Refclk1 : 125MHz Refclk2 : 156.25MHz 94 */ 95 static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, 96 {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, 97 {0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, 98 {0x15, 0xE8} }; 99 100 /* configuration values for IDT registers for Output Refclks: 101 * Refclk1 : 156.25MHz Refclk2 : 100MHz 102 */ 103 static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03}, 104 {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, 105 {0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C}, 106 {0x15, 0xE8} }; 107 108 /* configuration values for IDT registers for Output Refclks: 109 * Refclk1 : 156.25MHz Refclk2 : 125MHz 110 */ 111 static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03}, 112 {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, 113 {0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C}, 114 {0x15, 0xE8} }; 115 116 int set_serdes_refclk(u8 idt_addr, u8 serdes_num, 117 enum serdes_refclk refclk1, 118 enum serdes_refclk refclk2, u8 feedback); 119 120 #endif /*__IDT8T49N222A_SERDES_CLK_H_ */ 121