1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 * Author: Shaveta Leekha <shaveta@freescale.com> 5 */ 6 7 #include "idt8t49n222a_serdes_clk.h" 8 9 #define DEVICE_ID_REG 0x00 10 11 static int check_pll_status(u8 idt_addr) 12 { 13 u8 val = 0; 14 int ret; 15 16 ret = i2c_read(idt_addr, 0x17, 1, &val, 1); 17 if (ret < 0) { 18 printf("IDT:0x%x could not read status register from device.\n", 19 idt_addr); 20 return ret; 21 } 22 23 if (val & 0x04) { 24 debug("idt8t49n222a PLL is LOCKED: %x\n", val); 25 } else { 26 printf("idt8t49n222a PLL is not LOCKED: %x\n", val); 27 return -1; 28 } 29 30 return 0; 31 } 32 33 int set_serdes_refclk(u8 idt_addr, u8 serdes_num, 34 enum serdes_refclk refclk1, 35 enum serdes_refclk refclk2, u8 feedback) 36 { 37 u8 dev_id = 0; 38 int i, ret; 39 40 debug("IDT:Configuring idt8t49n222a device at I2C address: 0x%2x\n", 41 idt_addr); 42 43 ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1); 44 if (ret < 0) { 45 debug("IDT:0x%x could not read DEV_ID from device.\n", 46 idt_addr); 47 return ret; 48 } 49 50 if ((dev_id != 0x00) && (dev_id != 0x24) && (dev_id != 0x2a)) { 51 debug("IDT: device at address 0x%x is not idt8t49n222a.\n", 52 idt_addr); 53 } 54 55 if (serdes_num != 1 && serdes_num != 2) { 56 debug("serdes_num should be 1 for SerDes1 and" 57 " 2 for SerDes2.\n"); 58 return -1; 59 } 60 61 if ((refclk1 == SERDES_REFCLK_122_88 && refclk2 != SERDES_REFCLK_122_88) 62 || (refclk1 != SERDES_REFCLK_122_88 63 && refclk2 == SERDES_REFCLK_122_88)) { 64 debug("Only one refclk at 122.88MHz is not supported." 65 " Please set both refclk1 & refclk2 to 122.88MHz" 66 " or both not to 122.88MHz.\n"); 67 return -1; 68 } 69 70 if (refclk1 != SERDES_REFCLK_100 && refclk1 != SERDES_REFCLK_122_88 71 && refclk1 != SERDES_REFCLK_125 72 && refclk1 != SERDES_REFCLK_156_25) { 73 debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz" 74 " or 156.25MHz.\n"); 75 return -1; 76 } 77 78 if (refclk2 != SERDES_REFCLK_100 && refclk2 != SERDES_REFCLK_122_88 79 && refclk2 != SERDES_REFCLK_125 80 && refclk2 != SERDES_REFCLK_156_25) { 81 debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz" 82 " or 156.25MHz.\n"); 83 return -1; 84 } 85 86 if (feedback != 0 && feedback != 1) { 87 debug("valid values for feedback are 0(default) or 1.\n"); 88 return -1; 89 } 90 91 /* Configuring IDT for output refclks as 92 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz 93 */ 94 if (refclk1 == SERDES_REFCLK_122_88 && 95 refclk2 == SERDES_REFCLK_122_88) { 96 printf("Setting refclk1:122.88 and refclk2:122.88\n"); 97 for (i = 0; i < NUM_IDT_REGS; i++) 98 i2c_reg_write(idt_addr, idt_conf_122_88[i][0], 99 idt_conf_122_88[i][1]); 100 101 if (feedback) { 102 for (i = 0; i < NUM_IDT_REGS_FEEDBACK; i++) 103 i2c_reg_write(idt_addr, 104 idt_conf_122_88_feedback[i][0], 105 idt_conf_122_88_feedback[i][1]); 106 } 107 } 108 109 if (refclk1 != SERDES_REFCLK_122_88 && 110 refclk2 != SERDES_REFCLK_122_88) { 111 for (i = 0; i < NUM_IDT_REGS; i++) 112 i2c_reg_write(idt_addr, idt_conf_not_122_88[i][0], 113 idt_conf_not_122_88[i][1]); 114 } 115 116 /* Configuring IDT for output refclks as 117 * Refclk1 = 100MHz Refclk2 = 125MHz 118 */ 119 if (refclk1 == SERDES_REFCLK_100 && refclk2 == SERDES_REFCLK_125) { 120 printf("Setting refclk1:100 and refclk2:125\n"); 121 i2c_reg_write(idt_addr, 0x11, 0x10); 122 } 123 124 /* Configuring IDT for output refclks as 125 * Refclk1 = 125MHz Refclk2 = 125MHz 126 */ 127 if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_125) { 128 printf("Setting refclk1:125 and refclk2:125\n"); 129 i2c_reg_write(idt_addr, 0x10, 0x10); 130 i2c_reg_write(idt_addr, 0x11, 0x10); 131 } 132 133 /* Configuring IDT for output refclks as 134 * Refclk1 = 125MHz Refclk2 = 100MHz 135 */ 136 if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_100) { 137 printf("Setting refclk1:125 and refclk2:100\n"); 138 i2c_reg_write(idt_addr, 0x10, 0x10); 139 } 140 141 /* Configuring IDT for output refclks as 142 * Refclk1 = 156.25MHz Refclk2 = 156.25MHz 143 */ 144 if (refclk1 == SERDES_REFCLK_156_25 && 145 refclk2 == SERDES_REFCLK_156_25) { 146 printf("Setting refclk1:156.25 and refclk2:156.25\n"); 147 for (i = 0; i < NUM_IDT_REGS_156_25; i++) 148 i2c_reg_write(idt_addr, idt_conf_156_25[i][0], 149 idt_conf_156_25[i][1]); 150 } 151 152 /* Configuring IDT for output refclks as 153 * Refclk1 = 100MHz Refclk2 = 156.25MHz 154 */ 155 if (refclk1 == SERDES_REFCLK_100 && 156 refclk2 == SERDES_REFCLK_156_25) { 157 printf("Setting refclk1:100 and refclk2:156.25\n"); 158 for (i = 0; i < NUM_IDT_REGS_156_25; i++) 159 i2c_reg_write(idt_addr, idt_conf_100_156_25[i][0], 160 idt_conf_100_156_25[i][1]); 161 } 162 163 /* Configuring IDT for output refclks as 164 * Refclk1 = 125MHz Refclk2 = 156.25MHz 165 */ 166 if (refclk1 == SERDES_REFCLK_125 && 167 refclk2 == SERDES_REFCLK_156_25) { 168 printf("Setting refclk1:125 and refclk2:156.25\n"); 169 for (i = 0; i < NUM_IDT_REGS_156_25; i++) 170 i2c_reg_write(idt_addr, idt_conf_125_156_25[i][0], 171 idt_conf_125_156_25[i][1]); 172 } 173 174 /* Configuring IDT for output refclks as 175 * Refclk1 = 156.25MHz Refclk2 = 100MHz 176 */ 177 if (refclk1 == SERDES_REFCLK_156_25 && 178 refclk2 == SERDES_REFCLK_100) { 179 printf("Setting refclk1:156.25 and refclk2:100\n"); 180 for (i = 0; i < NUM_IDT_REGS_156_25; i++) 181 i2c_reg_write(idt_addr, idt_conf_156_25_100[i][0], 182 idt_conf_156_25_100[i][1]); 183 } 184 185 /* Configuring IDT for output refclks as 186 * Refclk1 = 156.25MHz Refclk2 = 125MHz 187 */ 188 if (refclk1 == SERDES_REFCLK_156_25 && 189 refclk2 == SERDES_REFCLK_125) { 190 printf("Setting refclk1:156.25 and refclk2:125\n"); 191 for (i = 0; i < NUM_IDT_REGS_156_25; i++) 192 i2c_reg_write(idt_addr, idt_conf_156_25_125[i][0], 193 idt_conf_156_25_125[i][1]); 194 } 195 196 /* waiting for maximum of 1 second if PLL doesn'r get locked 197 * initially. then check the status again. 198 */ 199 if (check_pll_status(idt_addr)) { 200 mdelay(1000); 201 if (check_pll_status(idt_addr)) 202 return -1; 203 } 204 205 return 0; 206 } 207