1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 26 #include "ics307_clk.h" 27 28 #if defined(CONFIG_FSL_NGPIXIS) 29 #include "ngpixis.h" 30 #define fpga_reg pixis 31 #elif defined(CONFIG_FSL_QIXIS) 32 #include "qixis.h" 33 #define fpga_reg ((struct qixis *)QIXIS_BASE) 34 #else 35 #include "pixis.h" 36 #define fpga_reg pixis 37 #endif 38 39 /* define for SYS CLK or CLK1Frequency */ 40 #define TTL 1 41 #define CLK2 0 42 #define CRYSTAL 0 43 #define MAX_VDW (511 + 8) 44 #define MAX_RDW (127 + 2) 45 #define MIN_VDW (4 + 8) 46 #define MIN_RDW (1 + 2) 47 #define NUM_OD_SETTING 8 48 /* 49 * These defines cover the industrial temperature range part, 50 * for commercial, change below to 400000 and 55000, respectively 51 */ 52 #define MAX_VCO 360000 53 #define MIN_VCO 60000 54 55 /* decode S[0-2] to Output Divider (OD) */ 56 static u8 ics307_s_to_od[] = { 57 10, 2, 8, 4, 5, 7, 3, 6 58 }; 59 60 /* 61 * Find one solution to generate required frequency for SYSCLK 62 * out_freq: KHz, required frequency to the SYSCLK 63 * the result will be retuned with component RDW, VDW, OD, TTL, 64 * CLK2 and crystal 65 */ 66 unsigned long ics307_sysclk_calculator(unsigned long out_freq) 67 { 68 const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ; 69 unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od; 70 unsigned long tmp_out, diff, result = 0; 71 int found = 0; 72 73 for (odp = 0; odp < NUM_OD_SETTING; odp++) { 74 od = ics307_s_to_od[odp]; 75 if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO) 76 continue; 77 for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) { 78 /* Calculate the VDW */ 79 vdw = out_freq * 1000 * od * rdw / (input_freq * 2); 80 if (vdw > MAX_VDW) 81 vdw = MAX_VDW; 82 if (vdw < MIN_VDW) 83 continue; 84 /* Calculate the temp out frequency */ 85 tmp_out = input_freq * 2 * vdw / (rdw * od * 1000); 86 diff = MAX(out_freq, tmp_out) - MIN(out_freq, tmp_out); 87 /* 88 * calculate the percent, the precision is 1/1000 89 * If greater than 1/1000, continue 90 * otherwise, we think the solution is we required 91 */ 92 if (diff * 1000 / out_freq > 1) 93 continue; 94 else { 95 s_vdw = vdw; 96 s_rdw = rdw; 97 s_odp = odp; 98 found = 1; 99 break; 100 } 101 } 102 } 103 104 if (found) 105 result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 | 106 CLK2 << 19 | TTL << 21 | CRYSTAL << 22; 107 108 debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8, 109 ics307_s_to_od[s_odp]); 110 return result; 111 } 112 113 /* 114 * Calculate frequency being generated by ICS307-02 clock chip based upon 115 * the control bytes being programmed into it. 116 */ 117 static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) 118 { 119 const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ; 120 unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 121 unsigned long rdw = cw2 & 0x7F; 122 unsigned long od = ics307_s_to_od[cw0 & 0x7]; 123 unsigned long freq; 124 125 /* 126 * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD) 127 * 128 * cw0: C1 C0 TTL F1 F0 S2 S1 S0 129 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 130 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 131 * 132 * R6:R0 = Reference Divider Word (RDW) 133 * V8:V0 = VCO Divider Word (VDW) 134 * S2:S0 = Output Divider Select (OD) 135 * F1:F0 = Function of CLK2 Output 136 * TTL = duty cycle 137 * C1:C0 = internal load capacitance for cyrstal 138 * 139 */ 140 141 freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od); 142 143 debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, 144 freq); 145 return freq; 146 } 147 148 unsigned long get_board_sys_clk(void) 149 { 150 return ics307_clk_freq( 151 in_8(&fpga_reg->sclk[0]), 152 in_8(&fpga_reg->sclk[1]), 153 in_8(&fpga_reg->sclk[2])); 154 } 155 156 unsigned long get_board_ddr_clk(void) 157 { 158 return ics307_clk_freq( 159 in_8(&fpga_reg->dclk[0]), 160 in_8(&fpga_reg->dclk[1]), 161 in_8(&fpga_reg->dclk[2])); 162 } 163