1 /* 2 * Copyright 2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 26 #include "ics307_clk.h" 27 28 #ifdef CONFIG_FSL_NGPIXIS 29 #include "ngpixis.h" 30 #else 31 #include "pixis.h" 32 #endif 33 34 /* define for SYS CLK or CLK1Frequency */ 35 #define TTL 1 36 #define CLK2 0 37 #define CRYSTAL 0 38 #define MAX_VDW (511 + 8) 39 #define MAX_RDW (127 + 2) 40 #define MIN_VDW (4 + 8) 41 #define MIN_RDW (1 + 2) 42 #define NUM_OD_SETTING 8 43 /* 44 * These defines cover the industrial temperature range part, 45 * for commercial, change below to 400000 and 55000, respectively 46 */ 47 #define MAX_VCO 360000 48 #define MIN_VCO 60000 49 50 /* decode S[0-2] to Output Divider (OD) */ 51 static u8 ics307_s_to_od[] = { 52 10, 2, 8, 4, 5, 7, 3, 6 53 }; 54 55 /* 56 * Find one solution to generate required frequency for SYSCLK 57 * out_freq: KHz, required frequency to the SYSCLK 58 * the result will be retuned with component RDW, VDW, OD, TTL, 59 * CLK2 and crystal 60 */ 61 unsigned long ics307_sysclk_calculator(unsigned long out_freq) 62 { 63 const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ; 64 unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od; 65 unsigned long tmp_out, diff, result = 0; 66 int found = 0; 67 68 for (odp = 0; odp < NUM_OD_SETTING; odp++) { 69 od = ics307_s_to_od[odp]; 70 if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO) 71 continue; 72 for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) { 73 /* Calculate the VDW */ 74 vdw = out_freq * 1000 * od * rdw / (input_freq * 2); 75 if (vdw > MAX_VDW) 76 vdw = MAX_VDW; 77 if (vdw < MIN_VDW) 78 continue; 79 /* Calculate the temp out frequency */ 80 tmp_out = input_freq * 2 * vdw / (rdw * od * 1000); 81 diff = MAX(out_freq, tmp_out) - MIN(out_freq, tmp_out); 82 /* 83 * calculate the percent, the precision is 1/1000 84 * If greater than 1/1000, continue 85 * otherwise, we think the solution is we required 86 */ 87 if (diff * 1000 / out_freq > 1) 88 continue; 89 else { 90 s_vdw = vdw; 91 s_rdw = rdw; 92 s_odp = odp; 93 found = 1; 94 break; 95 } 96 } 97 } 98 99 if (found) 100 result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 | 101 CLK2 << 19 | TTL << 21 | CRYSTAL << 22; 102 103 debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8, 104 ics307_s_to_od[s_odp]); 105 return result; 106 } 107 108 /* 109 * Calculate frequency being generated by ICS307-02 clock chip based upon 110 * the control bytes being programmed into it. 111 */ 112 static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) 113 { 114 const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ; 115 unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 116 unsigned long rdw = cw2 & 0x7F; 117 unsigned long od = ics307_s_to_od[cw0 & 0x7]; 118 unsigned long freq; 119 120 /* 121 * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD) 122 * 123 * cw0: C1 C0 TTL F1 F0 S2 S1 S0 124 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 125 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 126 * 127 * R6:R0 = Reference Divider Word (RDW) 128 * V8:V0 = VCO Divider Word (VDW) 129 * S2:S0 = Output Divider Select (OD) 130 * F1:F0 = Function of CLK2 Output 131 * TTL = duty cycle 132 * C1:C0 = internal load capacitance for cyrstal 133 * 134 */ 135 136 freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od); 137 138 debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, 139 freq); 140 return freq; 141 } 142 143 unsigned long get_board_sys_clk(void) 144 { 145 return ics307_clk_freq( 146 in_8(&pixis->sclk[0]), 147 in_8(&pixis->sclk[1]), 148 in_8(&pixis->sclk[2])); 149 } 150 151 unsigned long get_board_ddr_clk(void) 152 { 153 return ics307_clk_freq( 154 in_8(&pixis->dclk[0]), 155 in_8(&pixis->dclk[1]), 156 in_8(&pixis->dclk[2])); 157 } 158