1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/io.h>
9 
10 #include "ics307_clk.h"
11 
12 #if defined(CONFIG_FSL_NGPIXIS)
13 #include "ngpixis.h"
14 #define fpga_reg pixis
15 #elif defined(CONFIG_FSL_QIXIS)
16 #include "qixis.h"
17 #define fpga_reg ((struct qixis *)QIXIS_BASE)
18 #else
19 #include "pixis.h"
20 #define fpga_reg pixis
21 #endif
22 
23 /* define for SYS CLK or CLK1Frequency */
24 #define TTL		1
25 #define CLK2		0
26 #define CRYSTAL		0
27 #define MAX_VDW		(511 + 8)
28 #define MAX_RDW		(127 + 2)
29 #define MIN_VDW		(4 + 8)
30 #define MIN_RDW		(1 + 2)
31 #define NUM_OD_SETTING	8
32 /*
33  * These defines cover the industrial temperature range part,
34  * for commercial, change below to 400000 and 55000, respectively
35  */
36 #define MAX_VCO		360000
37 #define MIN_VCO		60000
38 
39 /* decode S[0-2] to Output Divider (OD) */
40 static u8 ics307_s_to_od[] = {
41 	10, 2, 8, 4, 5, 7, 3, 6
42 };
43 
44 /*
45  * Find one solution to generate required frequency for SYSCLK
46  * out_freq: KHz, required frequency to the SYSCLK
47  * the result will be retuned with component RDW, VDW, OD, TTL,
48  * CLK2 and crystal
49  */
50 unsigned long ics307_sysclk_calculator(unsigned long out_freq)
51 {
52 	const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
53 	unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;
54 	unsigned long tmp_out, diff, result = 0;
55 	int found = 0;
56 
57 	for (odp = 0; odp < NUM_OD_SETTING; odp++) {
58 		od = ics307_s_to_od[odp];
59 		if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)
60 			continue;
61 		for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) {
62 			/* Calculate the VDW */
63 			vdw = out_freq * 1000 * od * rdw / (input_freq * 2);
64 			if (vdw > MAX_VDW)
65 				vdw = MAX_VDW;
66 			if (vdw < MIN_VDW)
67 				continue;
68 			/* Calculate the temp out frequency */
69 			tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
70 			diff = max(out_freq, tmp_out) - min(out_freq, tmp_out);
71 			/*
72 			 * calculate the percent, the precision is 1/1000
73 			 * If greater than 1/1000, continue
74 			 * otherwise, we think the solution is we required
75 			 */
76 			if (diff * 1000 / out_freq > 1)
77 				continue;
78 			else {
79 				s_vdw = vdw;
80 				s_rdw = rdw;
81 				s_odp = odp;
82 				found = 1;
83 				break;
84 			}
85 		}
86 	}
87 
88 	if (found)
89 		result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 |
90 			CLK2 << 19 | TTL << 21 | CRYSTAL << 22;
91 
92 	debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,
93 			ics307_s_to_od[s_odp]);
94 	return result;
95 }
96 
97 /*
98  * Calculate frequency being generated by ICS307-02 clock chip based upon
99  * the control bytes being programmed into it.
100  */
101 static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
102 {
103 	const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
104 	unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
105 	unsigned long rdw = cw2 & 0x7F;
106 	unsigned long od = ics307_s_to_od[cw0 & 0x7];
107 	unsigned long freq;
108 
109 	/*
110 	 * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
111 	 *
112 	 * cw0:  C1 C0 TTL F1 F0 S2 S1 S0
113 	 * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
114 	 * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
115 	 *
116 	 * R6:R0 = Reference Divider Word (RDW)
117 	 * V8:V0 = VCO Divider Word (VDW)
118 	 * S2:S0 = Output Divider Select (OD)
119 	 * F1:F0 = Function of CLK2 Output
120 	 * TTL = duty cycle
121 	 * C1:C0 = internal load capacitance for cyrstal
122 	 *
123 	 */
124 
125 	freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
126 
127 	debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
128 			freq);
129 	return freq;
130 }
131 
132 unsigned long get_board_sys_clk(void)
133 {
134 	return ics307_clk_freq(
135 			in_8(&fpga_reg->sclk[0]),
136 			in_8(&fpga_reg->sclk[1]),
137 			in_8(&fpga_reg->sclk[2]));
138 }
139 
140 unsigned long get_board_ddr_clk(void)
141 {
142 	return ics307_clk_freq(
143 			in_8(&fpga_reg->dclk[0]),
144 			in_8(&fpga_reg->dclk[1]),
145 			in_8(&fpga_reg->dclk[2]));
146 }
147