1 /* 2 * Copyright 2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 26 #include "ics307_clk.h" 27 28 #ifdef CONFIG_FSL_NGPIXIS 29 #include "ngpixis.h" 30 #else 31 #include "pixis.h" 32 #endif 33 34 /* decode S[0-2] to Output Divider (OD) */ 35 static u8 ics307_s_to_od[] = { 36 10, 2, 8, 4, 5, 7, 3, 6 37 }; 38 39 /* 40 * Calculate frequency being generated by ICS307-02 clock chip based upon 41 * the control bytes being programmed into it. 42 */ 43 static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) 44 { 45 const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ; 46 unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 47 unsigned long rdw = cw2 & 0x7F; 48 unsigned long od = ics307_s_to_od[cw0 & 0x7]; 49 unsigned long freq; 50 51 /* 52 * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD) 53 * 54 * cw0: C1 C0 TTL F1 F0 S2 S1 S0 55 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 56 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 57 * 58 * R6:R0 = Reference Divider Word (RDW) 59 * V8:V0 = VCO Divider Word (VDW) 60 * S2:S0 = Output Divider Select (OD) 61 * F1:F0 = Function of CLK2 Output 62 * TTL = duty cycle 63 * C1:C0 = internal load capacitance for cyrstal 64 * 65 */ 66 67 freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od); 68 69 debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, 70 freq); 71 return freq; 72 } 73 74 unsigned long get_board_sys_clk(void) 75 { 76 return ics307_clk_freq( 77 in_8(&pixis->sclk[0]), 78 in_8(&pixis->sclk[1]), 79 in_8(&pixis->sclk[2])); 80 } 81 82 unsigned long get_board_ddr_clk(void) 83 { 84 return ics307_clk_freq( 85 in_8(&pixis->dclk[0]), 86 in_8(&pixis->dclk[1]), 87 in_8(&pixis->dclk[2])); 88 } 89