1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_validate.h> 9 #include <fsl_sfp.h> 10 11 #ifdef CONFIG_LS102XA 12 #include <asm/arch/immap_ls102xa.h> 13 #endif 14 15 #if defined(CONFIG_MPC85xx) 16 #define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 17 #else 18 #define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR 19 #endif 20 21 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE 22 #define gur_in32(a) in_le32(a) 23 #else 24 #define gur_in32(a) in_be32(a) 25 #endif 26 27 /* Check the Boot Mode. If Secure, return 1 else return 0 */ 28 int fsl_check_boot_mode_secure(void) 29 { 30 uint32_t val; 31 struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); 32 struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR); 33 34 val = sfp_in32(&sfp_regs->ospr) & ITS_MASK; 35 if (val == ITS_MASK) 36 return 1; 37 38 #if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx) 39 /* For PBL based platforms check the SB_EN bit in RCWSR */ 40 val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK; 41 if (val == RCW_SB_EN_MASK) 42 return 1; 43 #endif 44 45 #if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET) 46 /* For Non-PBL Platforms, check the Device Status register 2*/ 47 val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK; 48 if (val != MPC85xx_PORDEVSR2_SBC_MASK) 49 return 1; 50 51 #endif 52 return 0; 53 } 54 55 int fsl_setenv_chain_of_trust(void) 56 { 57 /* Check Boot Mode 58 * If Boot Mode is Non-Secure, no changes are required 59 */ 60 if (fsl_check_boot_mode_secure() == 0) 61 return 0; 62 63 /* If Boot mode is Secure, set the environment variables 64 * bootdelay = 0 (To disable Boot Prompt) 65 * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) 66 */ 67 setenv("bootdelay", "0"); 68 setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD); 69 return 0; 70 } 71