10a6b2714SAneesh Bansal /* 20a6b2714SAneesh Bansal * Copyright 2015 Freescale Semiconductor, Inc. 30a6b2714SAneesh Bansal * 40a6b2714SAneesh Bansal * SPDX-License-Identifier: GPL-2.0+ 50a6b2714SAneesh Bansal */ 60a6b2714SAneesh Bansal 70a6b2714SAneesh Bansal #include <common.h> 80a6b2714SAneesh Bansal #include <fsl_validate.h> 90a6b2714SAneesh Bansal #include <fsl_sfp.h> 100a6b2714SAneesh Bansal 110a6b2714SAneesh Bansal #ifdef CONFIG_LS102XA 120a6b2714SAneesh Bansal #include <asm/arch/immap_ls102xa.h> 130a6b2714SAneesh Bansal #endif 140a6b2714SAneesh Bansal 150a6b2714SAneesh Bansal #if defined(CONFIG_MPC85xx) 160a6b2714SAneesh Bansal #define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 170a6b2714SAneesh Bansal #else 180a6b2714SAneesh Bansal #define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR 190a6b2714SAneesh Bansal #endif 200a6b2714SAneesh Bansal 210a6b2714SAneesh Bansal #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE 220a6b2714SAneesh Bansal #define gur_in32(a) in_le32(a) 230a6b2714SAneesh Bansal #else 240a6b2714SAneesh Bansal #define gur_in32(a) in_be32(a) 250a6b2714SAneesh Bansal #endif 260a6b2714SAneesh Bansal 270a6b2714SAneesh Bansal /* Check the Boot Mode. If Secure, return 1 else return 0 */ 280a6b2714SAneesh Bansal int fsl_check_boot_mode_secure(void) 290a6b2714SAneesh Bansal { 300a6b2714SAneesh Bansal uint32_t val; 310a6b2714SAneesh Bansal struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); 320a6b2714SAneesh Bansal struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR); 330a6b2714SAneesh Bansal 340a6b2714SAneesh Bansal val = sfp_in32(&sfp_regs->ospr) & ITS_MASK; 350a6b2714SAneesh Bansal if (val == ITS_MASK) 360a6b2714SAneesh Bansal return 1; 370a6b2714SAneesh Bansal 380a6b2714SAneesh Bansal #if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx) 390a6b2714SAneesh Bansal /* For PBL based platforms check the SB_EN bit in RCWSR */ 400a6b2714SAneesh Bansal val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK; 410a6b2714SAneesh Bansal if (val == RCW_SB_EN_MASK) 420a6b2714SAneesh Bansal return 1; 430a6b2714SAneesh Bansal #endif 440a6b2714SAneesh Bansal 450a6b2714SAneesh Bansal #if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET) 460a6b2714SAneesh Bansal /* For Non-PBL Platforms, check the Device Status register 2*/ 470a6b2714SAneesh Bansal val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK; 480a6b2714SAneesh Bansal if (val != MPC85xx_PORDEVSR2_SBC_MASK) 490a6b2714SAneesh Bansal return 1; 500a6b2714SAneesh Bansal 510a6b2714SAneesh Bansal #endif 520a6b2714SAneesh Bansal return 0; 530a6b2714SAneesh Bansal } 54*d0412885SAneesh Bansal 55*d0412885SAneesh Bansal int fsl_setenv_chain_of_trust(void) 56*d0412885SAneesh Bansal { 57*d0412885SAneesh Bansal /* Check Boot Mode 58*d0412885SAneesh Bansal * If Boot Mode is Non-Secure, no changes are required 59*d0412885SAneesh Bansal */ 60*d0412885SAneesh Bansal if (fsl_check_boot_mode_secure() == 0) 61*d0412885SAneesh Bansal return 0; 62*d0412885SAneesh Bansal 63*d0412885SAneesh Bansal /* If Boot mode is Secure, set the environment variables 64*d0412885SAneesh Bansal * bootdelay = 0 (To disable Boot Prompt) 65*d0412885SAneesh Bansal * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) 66*d0412885SAneesh Bansal */ 67*d0412885SAneesh Bansal setenv("bootdelay", "0"); 68*d0412885SAneesh Bansal setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD); 69*d0412885SAneesh Bansal return 0; 70*d0412885SAneesh Bansal } 71