1 /* 2 * Copyright 2006 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <pci.h> 9 10 /* Config the VIA chip */ 11 void mpc85xx_config_via(struct pci_controller *hose, 12 pci_dev_t dev, struct pci_config_table *tab) 13 { 14 pci_dev_t bridge; 15 unsigned int cmdstat; 16 17 /* Enable USB and IDE functions */ 18 pci_hose_write_config_byte(hose, dev, 0x48, 0x08); 19 20 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); 21 cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER; 22 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); 23 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 24 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 25 26 /* 27 * Force the backplane P2P bridge to have a window 28 * open from 0x00000000-0x00001fff in PCI I/O space. 29 * This allows legacy I/O (i8259, etc) on the VIA 30 * southbridge to be accessed. 31 */ 32 bridge = PCI_BDF(0,BRIDGE_ID,0); 33 pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); 34 pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); 35 pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); 36 pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0); 37 } 38 39 /* Function 1, IDE */ 40 void mpc85xx_config_via_usbide(struct pci_controller *hose, 41 pci_dev_t dev, struct pci_config_table *tab) 42 { 43 pciauto_config_device(hose, dev); 44 /* 45 * Since the P2P window was forced to cover the fixed 46 * legacy I/O addresses, it is necessary to manually 47 * place the base addresses for the IDE and USB functions 48 * within this window. 49 */ 50 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8); 51 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4); 52 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8); 53 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4); 54 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0); 55 } 56 57 /* Function 2, USB ports 0-1 */ 58 void mpc85xx_config_via_usb(struct pci_controller *hose, 59 pci_dev_t dev, struct pci_config_table *tab) 60 { 61 pciauto_config_device(hose, dev); 62 63 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0); 64 } 65 66 /* Function 3, USB ports 2-3 */ 67 void mpc85xx_config_via_usb2(struct pci_controller *hose, 68 pci_dev_t dev, struct pci_config_table *tab) 69 { 70 pciauto_config_device(hose, dev); 71 72 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80); 73 } 74 75 /* Function 5, Power Management */ 76 void mpc85xx_config_via_power(struct pci_controller *hose, 77 pci_dev_t dev, struct pci_config_table *tab) 78 { 79 pciauto_config_device(hose, dev); 80 81 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00); 82 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc); 83 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8); 84 } 85 86 /* Function 6, AC97 Interface */ 87 void mpc85xx_config_via_ac97(struct pci_controller *hose, 88 pci_dev_t dev, struct pci_config_table *tab) 89 { 90 pciauto_config_device(hose, dev); 91 92 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00); 93 } 94