1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2006 Freescale Semiconductor. 4 */ 5 6 #include <common.h> 7 #include <pci.h> 8 9 /* Config the VIA chip */ 10 void mpc85xx_config_via(struct pci_controller *hose, 11 pci_dev_t dev, struct pci_config_table *tab) 12 { 13 pci_dev_t bridge; 14 unsigned int cmdstat; 15 16 /* Enable USB and IDE functions */ 17 pci_hose_write_config_byte(hose, dev, 0x48, 0x08); 18 19 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); 20 cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER; 21 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); 22 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 23 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 24 25 /* 26 * Force the backplane P2P bridge to have a window 27 * open from 0x00000000-0x00001fff in PCI I/O space. 28 * This allows legacy I/O (i8259, etc) on the VIA 29 * southbridge to be accessed. 30 */ 31 bridge = PCI_BDF(0,BRIDGE_ID,0); 32 pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); 33 pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); 34 pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); 35 pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0); 36 } 37 38 /* Function 1, IDE */ 39 void mpc85xx_config_via_usbide(struct pci_controller *hose, 40 pci_dev_t dev, struct pci_config_table *tab) 41 { 42 pciauto_config_device(hose, dev); 43 /* 44 * Since the P2P window was forced to cover the fixed 45 * legacy I/O addresses, it is necessary to manually 46 * place the base addresses for the IDE and USB functions 47 * within this window. 48 */ 49 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8); 50 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4); 51 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8); 52 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4); 53 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0); 54 } 55 56 /* Function 2, USB ports 0-1 */ 57 void mpc85xx_config_via_usb(struct pci_controller *hose, 58 pci_dev_t dev, struct pci_config_table *tab) 59 { 60 pciauto_config_device(hose, dev); 61 62 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0); 63 } 64 65 /* Function 3, USB ports 2-3 */ 66 void mpc85xx_config_via_usb2(struct pci_controller *hose, 67 pci_dev_t dev, struct pci_config_table *tab) 68 { 69 pciauto_config_device(hose, dev); 70 71 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80); 72 } 73 74 /* Function 5, Power Management */ 75 void mpc85xx_config_via_power(struct pci_controller *hose, 76 pci_dev_t dev, struct pci_config_table *tab) 77 { 78 pciauto_config_device(hose, dev); 79 80 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00); 81 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc); 82 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8); 83 } 84 85 /* Function 6, AC97 Interface */ 86 void mpc85xx_config_via_ac97(struct pci_controller *hose, 87 pci_dev_t dev, struct pci_config_table *tab) 88 { 89 pciauto_config_device(hose, dev); 90 91 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00); 92 } 93