1 /* 2 * Copyright 2006 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <pci.h> 25 26 /* Config the VIA chip */ 27 void mpc85xx_config_via(struct pci_controller *hose, 28 pci_dev_t dev, struct pci_config_table *tab) 29 { 30 pci_dev_t bridge; 31 unsigned int cmdstat; 32 33 /* Enable USB and IDE functions */ 34 pci_hose_write_config_byte(hose, dev, 0x48, 0x08); 35 36 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); 37 cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER; 38 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); 39 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 40 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 41 42 /* 43 * Force the backplane P2P bridge to have a window 44 * open from 0x00000000-0x00001fff in PCI I/O space. 45 * This allows legacy I/O (i8259, etc) on the VIA 46 * southbridge to be accessed. 47 */ 48 bridge = PCI_BDF(0,BRIDGE_ID,0); 49 pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); 50 pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); 51 pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); 52 pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0); 53 } 54 55 /* Function 1, IDE */ 56 void mpc85xx_config_via_usbide(struct pci_controller *hose, 57 pci_dev_t dev, struct pci_config_table *tab) 58 { 59 pciauto_config_device(hose, dev); 60 /* 61 * Since the P2P window was forced to cover the fixed 62 * legacy I/O addresses, it is necessary to manually 63 * place the base addresses for the IDE and USB functions 64 * within this window. 65 */ 66 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8); 67 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4); 68 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8); 69 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4); 70 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0); 71 } 72 73 /* Function 2, USB ports 0-1 */ 74 void mpc85xx_config_via_usb(struct pci_controller *hose, 75 pci_dev_t dev, struct pci_config_table *tab) 76 { 77 pciauto_config_device(hose, dev); 78 79 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0); 80 } 81 82 /* Function 3, USB ports 2-3 */ 83 void mpc85xx_config_via_usb2(struct pci_controller *hose, 84 pci_dev_t dev, struct pci_config_table *tab) 85 { 86 pciauto_config_device(hose, dev); 87 88 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80); 89 } 90 91 /* Function 5, Power Management */ 92 void mpc85xx_config_via_power(struct pci_controller *hose, 93 pci_dev_t dev, struct pci_config_table *tab) 94 { 95 pciauto_config_device(hose, dev); 96 97 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00); 98 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc); 99 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8); 100 } 101 102 /* Function 6, AC97 Interface */ 103 void mpc85xx_config_via_ac97(struct pci_controller *hose, 104 pci_dev_t dev, struct pci_config_table *tab) 105 { 106 pciauto_config_device(hose, dev); 107 108 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00); 109 } 110