1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/mmu.h> 9 10 struct fsl_e_tlb_entry tlb_table[] = { 11 /* TLB 0 - for temp stack in cache */ 12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 13 MAS3_SX|MAS3_SW|MAS3_SR, 0, 14 0, 0, BOOKE_PAGESZ_4K, 0), 15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 16 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 17 MAS3_SX|MAS3_SW|MAS3_SR, 0, 18 0, 0, BOOKE_PAGESZ_4K, 0), 19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 20 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21 MAS3_SX|MAS3_SW|MAS3_SR, 0, 22 0, 0, BOOKE_PAGESZ_4K, 0), 23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 24 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25 MAS3_SX|MAS3_SW|MAS3_SR, 0, 26 0, 0, BOOKE_PAGESZ_4K, 0), 27 28 /* TLB 1 */ 29 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 30 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 31 0, 0, BOOKE_PAGESZ_1M, 1), 32 33 #ifndef CONFIG_SPL_BUILD 34 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 35 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 36 0, 1, BOOKE_PAGESZ_64M, 1), 37 38 #ifdef CONFIG_PCI 39 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 40 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 41 0, 2, BOOKE_PAGESZ_256M, 1), 42 43 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 44 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 45 0, 3, BOOKE_PAGESZ_256K, 1), 46 #endif 47 #endif 48 49 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 50 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 51 0, 4, BOOKE_PAGESZ_64K, 1), 52 53 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 54 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 55 0, 5, BOOKE_PAGESZ_64K, 1), 56 57 SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, 58 CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, 59 MAS3_SX|MAS3_SW|MAS3_SR, 0, 60 0, 6, BOOKE_PAGESZ_256K, 1), 61 SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000, 62 CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000, 63 MAS3_SX|MAS3_SW|MAS3_SR, 0, 64 0, 7, BOOKE_PAGESZ_256K, 1), 65 66 #if defined(CONFIG_SYS_RAMBOOT) || \ 67 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) 68 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, 69 CONFIG_SYS_DDR_SDRAM_BASE, 70 MAS3_SX|MAS3_SW|MAS3_SR, 0, 71 0, 8, BOOKE_PAGESZ_256M, 1), 72 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, 73 CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, 74 MAS3_SX|MAS3_SW|MAS3_SR, 0, 75 0, 9, BOOKE_PAGESZ_256M, 1), 76 #endif 77 78 #ifdef CONFIG_SYS_INIT_L2_ADDR 79 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 80 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 81 0, 12, BOOKE_PAGESZ_256K, 1) 82 #endif 83 }; 84 85 int num_tlb_entries = ARRAY_SIZE(tlb_table); 86