1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/mmu.h> 9 10 struct fsl_e_tlb_entry tlb_table[] = { 11 /* TLB 0 - for temp stack in cache */ 12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 13 MAS3_SX|MAS3_SW|MAS3_SR, 0, 14 0, 0, BOOKE_PAGESZ_4K, 0), 15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 16 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 17 MAS3_SX|MAS3_SW|MAS3_SR, 0, 18 0, 0, BOOKE_PAGESZ_4K, 0), 19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 20 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21 MAS3_SX|MAS3_SW|MAS3_SR, 0, 22 0, 0, BOOKE_PAGESZ_4K, 0), 23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 24 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25 MAS3_SX|MAS3_SW|MAS3_SR, 0, 26 0, 0, BOOKE_PAGESZ_4K, 0), 27 28 /* TLB 1 */ 29 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 30 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 31 0, 0, BOOKE_PAGESZ_1M, 1), 32 33 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 34 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 35 0, 1, BOOKE_PAGESZ_64M, 1), 36 37 #ifdef CONFIG_PCI 38 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 39 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 40 0, 2, BOOKE_PAGESZ_256M, 1), 41 42 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 43 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 44 0, 3, BOOKE_PAGESZ_256K, 1), 45 #endif 46 47 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 48 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 49 0, 4, BOOKE_PAGESZ_64K, 1), 50 51 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 52 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 53 0, 5, BOOKE_PAGESZ_64K, 1), 54 55 SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, 56 CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, 57 MAS3_SX|MAS3_SW|MAS3_SR, 0, 58 0, 6, BOOKE_PAGESZ_256K, 1), 59 SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000, 60 CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000, 61 MAS3_SX|MAS3_SW|MAS3_SR, 0, 62 0, 7, BOOKE_PAGESZ_256K, 1), 63 64 #ifdef CONFIG_SYS_RAMBOOT 65 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, 66 CONFIG_SYS_DDR_SDRAM_BASE, 67 MAS3_SX|MAS3_SW|MAS3_SR, 0, 68 0, 8, BOOKE_PAGESZ_256M, 1), 69 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, 70 CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, 71 MAS3_SX|MAS3_SW|MAS3_SR, 0, 72 0, 9, BOOKE_PAGESZ_256M, 1), 73 #endif 74 }; 75 76 int num_tlb_entries = ARRAY_SIZE(tlb_table); 77