1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <i2c.h> 8 #include <asm/fsl_law.h> 9 #include <fsl_ddr_sdram.h> 10 #include <fsl_ddr_dimm_params.h> 11 12 #include "cpld.h" 13 14 #define C29XPCIE_HARDWARE_REVA 0x40 15 /* 16 * Micron MT41J128M16HA-15E 17 * */ 18 dimm_params_t ddr_raw_timing = { 19 .n_ranks = 1, 20 .rank_density = 536870912u, 21 .capacity = 536870912u, 22 .primary_sdram_width = 32, 23 .ec_sdram_width = 8, 24 .registered_dimm = 0, 25 .mirrored_dimm = 0, 26 .n_row_addr = 14, 27 .n_col_addr = 10, 28 .n_banks_per_sdram_device = 8, 29 .edc_config = 2, 30 .burst_lengths_bitmask = 0x0c, 31 32 .tckmin_x_ps = 1650, 33 .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */ 34 .taa_ps = 14050, 35 .twr_ps = 15000, 36 .trcd_ps = 13500, 37 .trrd_ps = 75000, 38 .trp_ps = 13500, 39 .tras_ps = 40000, 40 .trc_ps = 49500, 41 .trfc_ps = 160000, 42 .twtr_ps = 75000, 43 .trtp_ps = 75000, 44 .refresh_rate_ps = 7800000, 45 .tfaw_ps = 30000, 46 }; 47 48 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 49 unsigned int controller_number, 50 unsigned int dimm_number) 51 { 52 const char dimm_model[] = "Fixed DDR on board"; 53 54 if ((controller_number == 0) && (dimm_number == 0)) { 55 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 56 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 57 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 58 } 59 60 return 0; 61 } 62 63 void fsl_ddr_board_options(memctl_options_t *popts, 64 dimm_params_t *pdimm, 65 unsigned int ctrl_num) 66 { 67 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 68 int i; 69 70 popts->clk_adjust = 4; 71 popts->cpo_override = 0x1f; 72 popts->write_data_delay = 4; 73 popts->half_strength_driver_enable = 1; 74 popts->bstopre = 0x3cf; 75 popts->quad_rank_present = 1; 76 popts->rtt_override = 1; 77 popts->rtt_override_value = 1; 78 popts->dynamic_power = 1; 79 /* Write leveling override */ 80 popts->wrlvl_en = 1; 81 popts->wrlvl_override = 1; 82 popts->wrlvl_sample = 0xf; 83 popts->wrlvl_start = 0x4; 84 popts->trwt_override = 1; 85 popts->trwt = 0; 86 87 if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA) 88 popts->ecc_mode = 0; 89 90 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 91 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; 92 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; 93 } 94 } 95 96 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) 97 { 98 int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd, 99 sizeof(generic_spd_eeprom_t)); 100 101 if (ret) { 102 printf("DDR: failed to read SPD from address %u\n", 103 i2c_address); 104 memset(spd, 0, sizeof(generic_spd_eeprom_t)); 105 } 106 } 107