1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/fsl_law.h> 9 #include <asm/fsl_ddr_sdram.h> 10 #include <asm/fsl_ddr_dimm_params.h> 11 12 /* 13 * Micron MT41J128M16HA-15E 14 * */ 15 dimm_params_t ddr_raw_timing = { 16 .n_ranks = 1, 17 .rank_density = 536870912u, 18 .capacity = 536870912u, 19 .primary_sdram_width = 32, 20 .ec_sdram_width = 8, 21 .registered_dimm = 0, 22 .mirrored_dimm = 0, 23 .n_row_addr = 14, 24 .n_col_addr = 10, 25 .n_banks_per_sdram_device = 8, 26 .edc_config = 2, 27 .burst_lengths_bitmask = 0x0c, 28 29 .tCKmin_X_ps = 1650, 30 .caslat_X = 0x7e << 4, /* 5,6,7,8,9,10 */ 31 .tAA_ps = 14050, 32 .tWR_ps = 15000, 33 .tRCD_ps = 13500, 34 .tRRD_ps = 75000, 35 .tRP_ps = 13500, 36 .tRAS_ps = 40000, 37 .tRC_ps = 49500, 38 .tRFC_ps = 160000, 39 .tWTR_ps = 75000, 40 .tRTP_ps = 75000, 41 .refresh_rate_ps = 7800000, 42 .tFAW_ps = 30000, 43 }; 44 45 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 46 unsigned int controller_number, 47 unsigned int dimm_number) 48 { 49 const char dimm_model[] = "Fixed DDR on board"; 50 51 if ((controller_number == 0) && (dimm_number == 0)) { 52 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 53 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 54 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 55 } 56 57 return 0; 58 } 59 60 void fsl_ddr_board_options(memctl_options_t *popts, 61 dimm_params_t *pdimm, 62 unsigned int ctrl_num) 63 { 64 int i; 65 popts->clk_adjust = 2; 66 popts->cpo_override = 0x1f; 67 popts->write_data_delay = 4; 68 popts->half_strength_driver_enable = 1; 69 popts->bstopre = 0x3cf; 70 popts->quad_rank_present = 1; 71 popts->rtt_override = 1; 72 popts->rtt_override_value = 1; 73 popts->dynamic_power = 1; 74 /* Write leveling override */ 75 popts->wrlvl_en = 1; 76 popts->wrlvl_override = 1; 77 popts->wrlvl_sample = 0xf; 78 popts->wrlvl_start = 0x4; 79 popts->trwt_override = 1; 80 popts->trwt = 0; 81 82 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 83 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; 84 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; 85 } 86 } 87