xref: /openbmc/u-boot/board/freescale/c29xpcie/README (revision b3820ba9)
1Overview
2=========
3C29XPCIE board is a series of Freescale PCIe add-in cards to perform
4as public key crypto accelerator or secure key management module.
5It includes C293PCIE board, C293PCIE board and C291PCIE board.
6The Freescale C29x family is a high performance crypto co-processor.
7It combines a single e500v2 core with necessary SEC engines.
8(maximum core frequency 1000/1200 MHz).
9
10The C29xPCIE board features are as follows:
11Memory subsystem:
12	- 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
13	- 64 Mbyte NOR flash single-chip memory
14	- 4 Gbyte NAND flash memory
15	- 1 Mbit AT24C1024 I2C EEPROM
16	- 16 Mbyte SPI memory
17
18Interfaces:
19	- 10/100/1000 BaseT Ethernet ports:
20		- eTSEC1, RGMII: one 10/100/1000 port
21		- eTSEC2, RGMII: one 10/100/1000 port
22	- DUART interface:
23		- DUART interface: supports two UARTs up to 115200 bps for
24		   console display
25
26Board connectors:
27	- Mini-ITX power supply connector
28	- JTAG/COP for debugging
29
30Physical Memory Map on C29xPCIE
31===============================
32Address Start   Address End   Memory type
330x0_0000_0000 - 0x0_1fff_ffff   512MB DDR
340xc_0000_0000 - 0xc_8fff_ffff   256MB PCIE memory
350xf_ec00_0000 - 0xf_efff_ffff   64MB NOR flash
360xf_ffb0_0000 - 0xf_ffb7_ffff   512KB SRAM
370xf_ffc0_0000 - 0xf_ffc0_ffff   64KB PCIE IO
380xf_ffdf_0000 - 0xf_ffdf_0fff   4KB CPLD
390xf_ffe0_0000 - 0xf_ffef_ffff   1MB CCSR
40
41Serial Port Configuration on C29xPCIE
42=====================================
43Configure the serial port of the attached computer with the following values:
44	-Data rate: 115200 bps
45	-Number of data bits: 8
46	-Parity: None
47	-Number of Stop bits: 1
48	-Flow Control: Hardware/None
49
50Settings of DIP-switch
51======================
52  SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
53  SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
54Note: 1 stands for 'off', 0 stands for 'on'
55
56Build and program U-Boot to NOR flash
57==================================
581. Build u-boot.bin image example:
59	export ARCH=powerpc
60	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
61	make C293PCIE
62
632. Program u-boot.bin into NOR flash
64	=> tftp $loadaddr $uboot
65	=> protect off eff40000 +$filesize
66	=> erase eff40000 +$filesize
67	=> cp.b $loadaddr eff40000 $filesize
68
693. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
70
71Alternate NOR bank
72==================
73There are four banks in C29XPCIE board, example to change bank booting:
741. Program u-boot.bin into alternate NOR bank
75	=> tftp $loadaddr $uboot
76	=> protect off e9f40000 +$filesize
77	=> erase e9f40000 +$filesize
78	=> cp.b $loadaddr e9f40000 $filesize
79
802. Switch to alternate NOR bank
81	=> cpld_cmd reset altbank [bank]
82	- [bank] bank value select 1-4
83	- bank 1 on the flash 0x0000000~0x0ffffff
84	- bank 2 on the flash 0x1000000~0x1ffffff
85	- bank 3 on the flash 0x2000000~0x2ffffff
86	- bank 4 on the flash 0x3000000~0x3ffffff
87	or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.
88
89Build and program U-Boot to SPI flash
90==================================
911. Build u-boot-spi.bin image
92	make C29xPCIE_SPIFLASH_config; make
93	Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.
94
952. Program u-boot-spi.bin into SPI flash
96	=> tftp $loadaddr $uboot-spi
97	=> sf erase 0 100000
98	=> sf write $loadaddr 0 $filesize
99
1003. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.
101