1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <asm/mmu.h> 8 9 struct fsl_e_tlb_entry tlb_table[] = { 10 /* TLB 0 - for temp stack in cache */ 11 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 12 MAS3_SX|MAS3_SW|MAS3_SR, 0, 13 0, 0, BOOKE_PAGESZ_4K, 0), 14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 15 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 16 MAS3_SX|MAS3_SW|MAS3_SR, 0, 17 0, 0, BOOKE_PAGESZ_4K, 0), 18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 19 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 20 MAS3_SX|MAS3_SW|MAS3_SR, 0, 21 0, 0, BOOKE_PAGESZ_4K, 0), 22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 23 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 24 MAS3_SX|MAS3_SW|MAS3_SR, 0, 25 0, 0, BOOKE_PAGESZ_4K, 0), 26 27 /* TLB 1 */ 28 /* *I*** - Covers boot page */ 29 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 30 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 31 0, 0, BOOKE_PAGESZ_4K, 1), 32 #ifdef CONFIG_SPL_NAND_BOOT 33 SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, 34 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 35 0, 10, BOOKE_PAGESZ_4K, 1), 36 #endif 37 38 /* *I*G* - CCSRBAR (PA) */ 39 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 40 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 41 0, 1, BOOKE_PAGESZ_1M, 1), 42 43 /* CCSRBAR (DSP) */ 44 SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, 45 CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, 46 MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1), 47 48 #ifndef CONFIG_SPL_BUILD 49 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 50 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 51 0, 3, BOOKE_PAGESZ_64M, 1), 52 53 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000, 54 CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, 55 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 56 0, 4, BOOKE_PAGESZ_64M, 1), 57 58 #ifdef CONFIG_PCI 59 /* *I*G* - PCI */ 60 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 61 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 62 0, 6, BOOKE_PAGESZ_256M, 1), 63 64 /* *I*G* - PCI I/O */ 65 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 66 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 67 0, 7, BOOKE_PAGESZ_64K, 1), 68 #endif 69 #endif 70 71 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) 72 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 73 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 74 0, 8, BOOKE_PAGESZ_1G, 1), 75 #endif 76 77 #ifdef CONFIG_SYS_FPGA_BASE 78 /* *I*G - Board FPGA */ 79 SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS, 80 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 81 0, 9, BOOKE_PAGESZ_256K, 1), 82 #endif 83 84 #ifdef CONFIG_SYS_NAND_BASE_PHYS 85 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 86 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 87 0, 5, BOOKE_PAGESZ_1M, 1), 88 #endif 89 }; 90 91 int num_tlb_entries = ARRAY_SIZE(tlb_table); 92